mirror of https://github.com/zxdos/zxuno.git
62 lines
1.8 KiB
Verilog
62 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 00:24:56 05/08/2016
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// Design Name:
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// Module Name: control_enable_options
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module control_enable_options(
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output wire oe_n,
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output wire disable_ay,
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output wire disable_turboay,
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output wire disable_7ffd,
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output wire disable_1ffd,
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output wire disable_romsel7f,
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output wire disable_romsel1f,
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output wire enable_timexmmu,
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output wire disable_spisd
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);
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parameter DEVOPTIONS = 8'h0E;
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assign oe_n = ~(zxuno_addr == DEVOPTIONS && zxuno_regrd == 1'b1);
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reg [7:0] devoptions = 8'h00; // initial value
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assign disable_ay = devoptions[0];
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assign disable_turboay = devoptions[1];
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assign disable_7ffd = devoptions[2];
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assign disable_1ffd = devoptions[3];
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assign disable_romsel7f = devoptions[4];
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assign disable_romsel1f = devoptions[5];
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assign enable_timexmmu = devoptions[6];
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assign disable_spisd = devoptions[7];
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always @(posedge clk) begin
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if (rst_n == 1'b0)
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devoptions <= 8'h00; // or after a hardware reset (not implemented yet)
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else if (zxuno_addr == DEVOPTIONS && zxuno_regwr == 1'b1)
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devoptions <= din;
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dout <= devoptions;
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end
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endmodule
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