mirror of https://github.com/zxdos/zxuno.git
120 lines
4.3 KiB
VHDL
120 lines
4.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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-- This is input-only for the time being
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entity ps2_intf is
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generic (filter_length : positive := 8);
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port(
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CLK : in std_logic;
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nRESET : in std_logic;
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-- PS/2 interface (could be bi-dir)
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PS2_CLK : in std_logic;
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PS2_DATA : in std_logic;
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-- Byte-wide data interface - only valid for one clock
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-- so must be latched externally if required
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DATA : out std_logic_vector(7 downto 0);
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VALID : out std_logic;
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error : out std_logic
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);
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end ps2_intf;
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architecture ps2_intf_arch of ps2_intf is
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--subtype filter_t is std_logic_vector(filter_length-1 downto 0);
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--signal clk_filter : filter_t;
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signal clk_filter : std_logic_vector(7 downto 0);
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signal ps2_clk_in : std_logic;
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signal ps2_dat_in : std_logic;
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-- Goes high when a clock falling edge is detected
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signal clk_edge : std_logic;
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signal bit_count : unsigned (3 downto 0);
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signal shiftreg : std_logic_vector(8 downto 0);
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signal parity : std_logic;
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begin
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-- Register input signals
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process(nRESET, CLK)
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begin
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if nRESET = '0' then
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ps2_clk_in <= '1';
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ps2_dat_in <= '1';
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clk_filter <= (others => '1');
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clk_edge <= '0';
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elsif rising_edge(CLK) then
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-- Register inputs (and filter clock)
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ps2_dat_in <= PS2_DATA;
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clk_filter <= PS2_CLK & clk_filter(7 downto 1);
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clk_edge <= '0';
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if clk_filter = x"ff" then
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-- Filtered clock is high
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ps2_clk_in <= '1';
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elsif clk_filter = x"00" then
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-- Filter clock is low, check for edge
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if ps2_clk_in = '1' then
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clk_edge <= '1';
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end if;
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ps2_clk_in <= '0';
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end if;
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end if;
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end process;
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-- Shift in keyboard data
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process(nRESET, CLK)
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begin
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if nRESET = '0' then
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bit_count <= (others => '0');
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shiftreg <= (others => '0');
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parity <= '0';
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DATA <= (others => '0');
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VALID <= '0';
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error <= '0';
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elsif rising_edge(CLK) then
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-- Clear flags
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VALID <= '0';
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error <= '0';
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if clk_edge = '1' then
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-- We have a new bit from the keyboard for processing
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if bit_count = 0 then
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-- Idle state, check for start bit (0) only and don't
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-- start counting bits until we get it
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parity <= '0';
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if ps2_dat_in = '0' then
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-- This is a start bit
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bit_count <= bit_count + 1;
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end if;
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else
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-- Running. 8-bit data comes in LSb first followed by
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-- a single stop bit (1)
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if bit_count < 10 then
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-- Shift in data and parity (9 bits)
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bit_count <= bit_count + 1;
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shiftreg <= ps2_dat_in & shiftreg(shiftreg'high downto 1);
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parity <= parity xor ps2_dat_in; -- Calculate parity
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elsif ps2_dat_in = '1' then
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-- Valid stop bit received
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bit_count <= (others => '0'); -- back to idle
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if parity = '1' then
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-- Parity correct, submit data to host
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DATA <= shiftreg(7 downto 0);
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VALID <= '1';
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else
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-- Error
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error <= '1';
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end if;
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else
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-- Invalid stop bit
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bit_count <= (others => '0'); -- back to idle
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error <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end ps2_intf_arch;
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