mirror of https://github.com/zxdos/zxuno.git
66 lines
1.1 KiB
Verilog
66 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:39:37 03/24/2011
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// Design Name: jace_en_fpga
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// Module Name: C:/proyectos_xilinx/fpga_ace/test_ace.v
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// Project Name: fpga_ace
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: jace_en_fpga
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module test_ace;
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// Inputs
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reg clk50mhz;
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reg reset;
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reg ear;
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// Outputs
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wire spk;
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wire mic;
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wire video;
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wire sync;
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// Instantiate the Unit Under Test (UUT)
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jace_en_fpga uut (
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.clk50mhz(clk50mhz),
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.reset(reset),
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.ear(ear),
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.spk(spk),
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.mic(mic),
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.video(video),
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.sync(sync)
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);
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initial begin
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// Initialize Inputs
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clk50mhz = 0;
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reset = 1;
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ear = 0;
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// Wait 100 ns for global reset to finish
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#1000;
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reset = 0;
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// Add stimulus here
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end
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always
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#77 clk50mhz = !clk50mhz;
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endmodule
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