mirror of https://github.com/zxdos/zxuno.git
66 lines
1.6 KiB
Verilog
66 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Miguel Angel Rodriguez Jodar
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//
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// Create Date: 03:22:12 07/25/2015
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// Design Name: SAM Coupé clone
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// Module Name: rom
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// Project Name: SAM Coupé clone
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// Target Devices: Spartan 6
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// Tool versions: ISE 12.4
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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(* rom_extract = "yes" *)
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(* rom_style = "block" *)
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module rom (
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input wire clk,
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input wire [14:0] a,
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output reg [7:0] dout
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);
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reg [7:0] mem[0:32767];
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//reg [7:0] mem[0:16383];
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initial begin
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`ifdef SYNTH
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$readmemh ("rom30.hex", mem);
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//$readmemh ("48.hex", mem);
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//$readmemh ("128k_paul_farrow.hex", mem);
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//$readmemh ("test48kmcleod.hex", mem);
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`else
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mem[ 0] = 8'd33;
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mem[ 1] = 8'd14;
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mem[ 2] = 8'd0;
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mem[ 3] = 8'd17;
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mem[ 4] = 8'd0;
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mem[ 5] = 8'd128;
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mem[ 6] = 8'd1;
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mem[ 7] = 8'd6;
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mem[ 8] = 8'd0;
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mem[ 9] = 8'd237;
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mem[10] = 8'd176;
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mem[11] = 8'd195;
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mem[12] = 8'd0;
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mem[13] = 8'd128;
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mem[14] = 8'd175;
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mem[15] = 8'd211;
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mem[16] = 8'd254;
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mem[17] = 8'd195;
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mem[18] = 8'd0;
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mem[19] = 8'd128;
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`endif
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end
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always @(posedge clk)
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dout <= mem[a];
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endmodule
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