mirror of https://github.com/zxdos/zxuno.git
89 lines
2.6 KiB
Verilog
89 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 03:05:03 06/28/2015
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// Design Name:
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// Module Name: nmievents
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module nmievents (
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input wire clk,
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input wire rst_n,
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//------------------------------
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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//------------------------------
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input wire [4:0] userevents,
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//------------------------------
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input wire [15:0] a,
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input wire m1_n,
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input wire mreq_n,
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input wire rd_n,
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output wire [7:0] dout,
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output wire oe_n,
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output reg nmiout_n,
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output reg page_configrom_active
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);
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parameter NMIEVENT = 8'h08;
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parameter IDLE = 1'd0,
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ABOUT_TO_EXIT = 1'd1;
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initial page_configrom_active = 1'b0;
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initial nmiout_n = 1'b1;
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reg state = IDLE;
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reg [7:0] nmieventreg = 8'h00;
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assign dout = nmieventreg;
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assign oe_n = ~(zxuno_addr == NMIEVENT && zxuno_regrd == 1'b1);
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always @(posedge clk) begin
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if (rst_n == 1'b0) begin
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nmieventreg <= 8'h00;
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page_configrom_active <= 1'b0;
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state <= IDLE;
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end
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else begin
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if (userevents != 5'b00000 && page_configrom_active == 1'b0) begin
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nmieventreg <= {3'b000, userevents};
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nmiout_n <= 1'b0;
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page_configrom_active <= 1'b1;
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state <= IDLE;
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end
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if (mreq_n == 1'b0 && m1_n == 1'b0 && a == 16'h0066 && page_configrom_active == 1'b1) // ya estamos en NMI
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nmiout_n <= 1'b1; // asi que desactivo la señal
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case (state)
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IDLE:
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begin
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if (mreq_n == 1'b0 && m1_n == 1'b0 && rd_n == 1'b0 && a==16'h006A && page_configrom_active == 1'b1)
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state <= ABOUT_TO_EXIT;
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end
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ABOUT_TO_EXIT:
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begin
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if (m1_n == 1'b1) begin
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page_configrom_active <= 1'b0;
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nmieventreg <= 8'h00;
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state <= IDLE;
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end
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end
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default: state <= IDLE;
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endcase
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end
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end
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endmodule
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