mirror of https://github.com/zxdos/zxuno.git
347 lines
10 KiB
Verilog
347 lines
10 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
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//
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// Company: Xilinx
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// Engineer: Karl Kurbjun and Carl Ribbing
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// Date: 2/19/2009
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// Design Name: PLL DRP
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// Module Name: top.v
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// Version: 1.0
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// Target Devices: Spartan 6 Family
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// Tool versions: L.68 (lin)
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// Description: This is a basic demonstration of the PLL_DRP
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// connectivity to the PLL_ADV.
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//
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// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
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// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
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// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
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// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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// APPLICATION OR STANDARD, XILINX IS MAKING NO
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// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
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// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
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// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
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// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
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// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
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// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
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// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
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// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE.
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//
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// (c) Copyright 2008 Xilinx, Inc.
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// All rights reserved.
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//
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1ps/1ps
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`default_nettype none
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module pll_top
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(
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// SSTEP is the input to start a reconfiguration. It should only be
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// pulsed for one clock cycle.
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input wire SSTEP,
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// STATE determines which state the PLL_ADV will be reconfigured to. A
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// value of 0 correlates to state 1, and a value of 1 correlates to state
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// 2.
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input wire [2:0] STATE,
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// RST will reset the entire reference design including the PLL_ADV
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input wire RST,
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// CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the
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// clock for the PLL_DRP module
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input wire CLKIN,
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// SRDY pulses for one clock cycle after the PLL_ADV is locked and the
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// PLL_DRP module is ready to start another re-configuration
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output wire SRDY,
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// These are the clock outputs from the PLL_ADV.
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output wire CLK0OUT,
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output wire CLK1OUT,
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output wire CLK2OUT,
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output wire CLK3OUT,
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output wire CLK4OUT,
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output wire CLK5OUT
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);
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// These signals are used as direct connections between the PLL_ADV and the
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// PLL_DRP.
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wire [15:0] di;
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wire [4:0] daddr;
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wire [15:0] dout;
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wire den;
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wire dwe;
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wire dclk;
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wire rst_pll;
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wire drdy;
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wire locked;
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// These signals are used for the BUFG's necessary for the design.
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wire clkfb_bufgout;
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wire clkfb_bufgin;
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wire clk0_bufgin;
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wire clk0_bufgout;
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wire clk1_bufgin;
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wire clk1_bufgout;
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wire clk2_bufgin;
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wire clk2_bufgout;
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wire clk3_bufgin;
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wire clk3_bufgout;
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wire clk4_bufgin;
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wire clk4_bufgout;
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wire clk5_bufgin;
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wire clk5_bufgout;
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// Global buffers used in design
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BUFG BUFG_FB (
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.O(clkfb_bufgout),
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.I(clkfb_bufgin)
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);
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BUFG BUFG_CLK0 (
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.O(CLK0OUT),
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.I(clk0_bufgin)
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);
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BUFG BUFG_CLK1 (
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.O(CLK1OUT),
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.I(clk1_bufgin)
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);
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BUFG BUFG_CLK2 (
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.O(CLK2OUT),
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.I(clk2_bufgin)
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);
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BUFG BUFG_CLK3 (
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.O(CLK3OUT),
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.I(clk3_bufgin)
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);
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BUFG BUFG_CLK4 (
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.O(CLK4OUT),
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.I(clk4_bufgin)
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);
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BUFG BUFG_CLK5 (
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.O(CLK5OUT),
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.I(clk5_bufgin)
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);
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// // ODDR registers used to output clocks
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//
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// ODDR2 #(
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// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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// .INIT(1'b0), // Sets initial state of the Q output to 1<>b0 or 1<>b1
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// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
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// ) ODDR2_CLK0 (
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// .Q(CLK0OUT), // 1-bit DDR output data
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// .C0(clk0_bufgout), // 1-bit clock input
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// .C1(~clk0_bufgout), // 1-bit clock input
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// .CE(1'b1), // 1-bit clock enable input
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// .D0(1'b1), // 1-bit data input (associated with C0)
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// .D1(1'b0), // 1-bit data input (associated with C1)
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// .R(RST), // 1-bit reset input
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// .S(1'b0) // 1-bit set input
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// );
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//
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// ODDR2 #(
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// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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// .INIT(1'b0), // Sets initial state of the Q output to 1<>b0 or 1<>b1
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// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
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// ) ODDR2_CLK1 (
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// .Q(CLK1OUT), // 1-bit DDR output data
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// .C0(clk1_bufgout), // 1-bit clock input
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// .C1(~clk1_bufgout), // 1-bit clock input
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// .CE(1'b1), // 1-bit clock enable input
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// .D0(1'b1), // 1-bit data input (associated with C0)
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// .D1(1'b0), // 1-bit data input (associated with C1)
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// .R(RST), // 1-bit reset input
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// .S(1'b0) // 1-bit set input
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// );
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//
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// ODDR2 #(
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// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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// .INIT(1'b0), // Sets initial state of the Q output to 1<>b0 or 1<>b1
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// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
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// ) ODDR2_CLK2 (
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// .Q(CLK2OUT), // 1-bit DDR output data
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// .C0(clk2_bufgout), // 1-bit clock input
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// .C1(~clk2_bufgout), // 1-bit clock input
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// .CE(1'b1), // 1-bit clock enable input
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// .D0(1'b1), // 1-bit data input (associated with C0)
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// .D1(1'b0), // 1-bit data input (associated with C1)
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// .R(RST), // 1-bit reset input
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// .S(1'b0) // 1-bit set input
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// );
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//
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// ODDR2 #(
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// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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// .INIT(1'b0), // Sets initial state of the Q output to 1<>b0 or 1<>b1
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// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
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// ) ODDR2_CLK3 (
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// .Q(CLK3OUT), // 1-bit DDR output data
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// .C0(clk3_bufgout), // 1-bit clock input
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// .C1(~clk3_bufgout), // 1-bit clock input
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// .CE(1'b1), // 1-bit clock enable input
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// .D0(1'b1), // 1-bit data input (associated with C0)
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// .D1(1'b0), // 1-bit data input (associated with C1)
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// .R(RST), // 1-bit reset input
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// .S(1'b0) // 1-bit set input
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// );
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//
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// ODDR2 #(
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// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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// .INIT(1'b0), // Sets initial state of the Q output to 1<>b0 or 1<>b1
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// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
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// ) ODDR2_CLK4 (
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// .Q(CLK4OUT), // 1-bit DDR output data
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// .C0(clk4_bufgout), // 1-bit clock input
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// .C1(~clk4_bufgout), // 1-bit clock input
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// .CE(1'b1), // 1-bit clock enable input
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// .D0(1'b1), // 1-bit data input (associated with C0)
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// .D1(1'b0), // 1-bit data input (associated with C1)
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// .R(RST), // 1-bit reset input
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// .S(1'b0) // 1-bit set input
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// );
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//
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// ODDR2 #(
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// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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// .INIT(1'b0), // Sets initial state of the Q output to 1<>b0 or 1<>b1
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// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
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// ) ODDR2_CLK5 (
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// .Q(CLK5OUT), // 1-bit DDR output data
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// .C0(clk5_bufgout), // 1-bit clock input
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// .C1(~clk5_bufgout), // 1-bit clock input
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// .CE(1'b1), // 1-bit clock enable input
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// .D0(1'b1), // 1-bit data input (associated with C0)
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// .D1(1'b0), // 1-bit data input (associated with C1)
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// .R(RST), // 1-bit reset input
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// .S(1'b0) // 1-bit set input
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// );
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// PLL_ADV that reconfiguration will take place on
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PLL_ADV #(
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.SIM_DEVICE("SPARTAN6"),
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.DIVCLK_DIVIDE(1), // 1 to 52
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.BANDWIDTH("LOW"), // "HIGH", "LOW" or "OPTIMIZED"
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// CLKFBOUT stuff
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.CLKFBOUT_MULT(14),
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.CLKFBOUT_PHASE(0.0),
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// Set the clock period (ns) of input clocks and reference jitter
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.REF_JITTER(0.100),
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.CLKIN1_PERIOD(20.000),
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.CLKIN2_PERIOD(20.000),
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// CLKOUT parameters:
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// DIVIDE: (1 to 128)
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// DUTY_CYCLE: (0.01 to 0.99) - This is dependent on the divide value.
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// PHASE: (0.0 to 360.0) - This is dependent on the divide value.
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.CLKOUT0_DIVIDE(25),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_DIVIDE(25),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_DIVIDE(25),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_DIVIDE(25),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_DIVIDE(25),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_DIVIDE(25),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0.0),
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// Set the compensation
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.COMPENSATION("SYSTEM_SYNCHRONOUS"),
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// PMCD stuff (not used)
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.EN_REL("FALSE"),
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.PLL_PMCD_MODE("FALSE"),
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.RST_DEASSERT_CLK("CLKIN1")
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) PLL_ADV_inst (
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.CLKFBDCM(),
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.CLKFBOUT(clkfb_bufgin),
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// CLK outputs
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.CLKOUT0(clk0_bufgin),
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.CLKOUT1(clk1_bufgin),
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.CLKOUT2(clk2_bufgin),
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.CLKOUT3(clk3_bufgin),
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.CLKOUT4(clk4_bufgin),
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.CLKOUT5(clk5_bufgin),
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// CLKOUTS to DCM
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.CLKOUTDCM0(),
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.CLKOUTDCM1(),
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.CLKOUTDCM2(),
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.CLKOUTDCM3(),
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.CLKOUTDCM4(),
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.CLKOUTDCM5(),
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// DRP Ports
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.DO(dout),
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.DRDY(drdy),
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.DADDR(daddr),
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.DCLK(dclk),
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.DEN(den),
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.DI(di),
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.DWE(dwe),
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.LOCKED(locked),
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.CLKFBIN(clkfb_bufgout),
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// Clock inputs
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.CLKIN1(CLKIN),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.REL(1'b0),
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.RST(rst_pll)
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);
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// PLL_DRP instance that will perform the reconfiguration operations
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pll_drp PLL_DRP_inst (
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// Top port connections
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.SADDR(STATE),
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.SEN(SSTEP),
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.RST(RST),
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.SRDY(SRDY),
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// Input from IBUFG
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.SCLK(CLKIN),
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// Direct connections to the PLL_ADV
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.DO(dout),
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.DRDY(drdy),
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.LOCKED(locked),
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.DWE(dwe),
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.DEN(den),
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.DADDR(daddr),
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.DI(di),
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.DCLK(dclk),
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.RST_PLL(rst_pll)
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);
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endmodule
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