mirror of https://github.com/zxdos/zxuno.git
36 lines
654 B
VHDL
36 lines
654 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity ram is
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port (
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clk: in STD_LOGIC;
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RD_n: in STD_LOGIC;
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WR_n: in STD_LOGIC;
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A: in STD_LOGIC_VECTOR (12 downto 0);
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D_in: in STD_LOGIC_VECTOR (7 downto 0);
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D_out: out STD_LOGIC_VECTOR (7 downto 0));
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end entity;
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architecture Behavioral of ram is
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begin
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ram_blocks:
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for i in 0 to 3 generate
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begin
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RAMB16_S2_inst : RAMB16_S2
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port map (
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CLK => clk,
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EN => '1',
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SSR => '0',
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WE => not WR_n,
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ADDR => a,
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DI => D_in((2*i+1) downto (2*i)),
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DO => D_out((2*i+1) downto (2*i))
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);
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end generate;
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end Behavioral;
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