mirror of https://github.com/zxdos/zxuno.git
136 lines
3.4 KiB
VHDL
136 lines
3.4 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity vdp_main is
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port (
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clk: in std_logic;
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vram_A: out std_logic_vector(13 downto 0);
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vram_D: in std_logic_vector(7 downto 0);
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cram_A: out std_logic_vector(4 downto 0);
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cram_D: in std_logic_vector(5 downto 0);
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x: unsigned(8 downto 0);
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y: unsigned(7 downto 0);
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color: out std_logic_vector (5 downto 0);
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-- display_on: in std_logic;
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mask_column0: in std_logic;
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overscan: in std_logic_vector (3 downto 0);
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bg_address: in std_logic_vector (2 downto 0);
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bg_scroll_x: in unsigned(7 downto 0);
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bg_scroll_y: in unsigned(7 downto 0);
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disable_hscroll: in std_logic;
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spr_address: in std_logic_vector (5 downto 0);
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spr_high_bit: in std_logic;
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-- spr_shift: in std_logic;
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spr_tall: in std_logic);
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end vdp_main;
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architecture Behavioral of vdp_main is
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component vdp_background is
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port (
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clk: in std_logic;
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reset: in std_logic;
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table_address: in std_logic_vector(13 downto 11);
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scroll_x: in unsigned(7 downto 0);
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disable_hscroll: in std_logic;
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y: in unsigned(7 downto 0);
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vram_A: out std_logic_vector(13 downto 0);
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vram_D: in std_logic_vector(7 downto 0);
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color: out std_logic_vector(4 downto 0);
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priority: out std_logic);
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end component;
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component vdp_sprites is
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port (
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clk: in std_logic;
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table_address: in std_logic_vector(13 downto 8);
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char_high_bit: in std_logic;
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tall: in std_logic;
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x: in unsigned(8 downto 0);
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y: in unsigned(7 downto 0);
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vram_A: out std_logic_vector(13 downto 0);
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vram_D: in std_logic_vector(7 downto 0);
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color: out std_logic_vector(3 downto 0));
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end component;
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signal bg_y: unsigned(7 downto 0);
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signal bg_vram_A: std_logic_vector(13 downto 0);
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signal bg_color: std_logic_vector(4 downto 0);
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signal bg_priority: std_logic;
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signal spr_vram_A: std_logic_vector(13 downto 0);
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signal spr_color: std_logic_vector(3 downto 0);
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signal line_reset: std_logic;
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begin
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process (y,bg_scroll_y)
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variable sum: unsigned(8 downto 0);
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begin
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sum := ('0'&y)+('0'&bg_scroll_y);
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if (sum>=224) then
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sum := sum-224;
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end if;
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bg_y <= sum(7 downto 0);
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end process;
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line_reset <= '1' when x=512-16 else '0';
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vdp_bg_inst: vdp_background
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port map (
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clk => clk,
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table_address => bg_address,
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reset => line_reset,
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disable_hscroll=> disable_hscroll,
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scroll_x => bg_scroll_x,
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y => bg_y,
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vram_A => bg_vram_A,
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vram_D => vram_D,
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color => bg_color,
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priority => bg_priority);
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vdp_spr_inst: vdp_sprites
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port map (
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clk => clk,
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table_address => spr_address,
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char_high_bit => spr_high_bit,
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tall => spr_tall,
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x => x,
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y => y,
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vram_A => spr_vram_A,
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vram_D => vram_D,
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color => spr_color);
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process (x, y, bg_priority, spr_color, bg_color, overscan)
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variable spr_active : boolean;
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variable bg_active : boolean;
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begin
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if x<256 and y<192 and (mask_column0='0' or x>=8) then
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spr_active := not (spr_color="0000");
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bg_active := not (bg_color(3 downto 0)="0000");
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if (bg_priority='0' and spr_active) or (bg_priority='1' and not bg_active) then
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cram_A <= "1"&spr_color;
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else
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cram_A <= bg_color;
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end if;
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else
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cram_A <= "1"&overscan;
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end if;
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end process;
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vram_A <= spr_vram_A when x>=256 and x<384 else bg_vram_A;
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color <= cram_D;
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end Behavioral;
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