mirror of https://github.com/zxdos/zxuno.git
319 lines
7.4 KiB
VHDL
319 lines
7.4 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity sms is
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port (
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clk: in STD_LOGIC;
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sram_we_n: out STD_LOGIC;
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sram_a: out STD_LOGIC_VECTOR(18 downto 0);
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ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
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-- j1_MDsel: out STD_LOGIC; --Q
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j1_up: in STD_LOGIC;
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j1_down: in STD_LOGIC;
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j1_left: in STD_LOGIC;
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j1_right: in STD_LOGIC;
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j1_tl: in STD_LOGIC;
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j1_tr: inout STD_LOGIC;
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audio_l: out STD_LOGIC;
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audio_r: out STD_LOGIC;
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red: buffer STD_LOGIC_VECTOR(2 downto 0);
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green: buffer STD_LOGIC_VECTOR(2 downto 0);
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blue: buffer STD_LOGIC_VECTOR(2 downto 0);
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hsync: buffer STD_LOGIC;
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vsync: buffer STD_LOGIC;
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dred: out STD_LOGIC_VECTOR(2 downto 0);
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dgreen: out STD_LOGIC_VECTOR(2 downto 0);
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dblue: out STD_LOGIC_VECTOR(2 downto 0);
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dhsync: out STD_LOGIC;
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dvsync: out STD_LOGIC;
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spi_do: in STD_LOGIC;
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spi_sclk: out STD_LOGIC;
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spi_di: out STD_LOGIC;
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spi_cs_n: buffer STD_LOGIC;
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led: out STD_LOGIC;
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ps2_clk: in std_logic;
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ps2_data: in std_logic;
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NTSC: out std_logic; --Q
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PAL: out std_logic --Q
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);
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end sms;
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architecture Behavioral of sms is
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component clock is
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port (
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clk_in: in std_logic;
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sel_pclock: in std_logic;
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clk_cpu: out std_logic;
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clk16: out std_logic;
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clk8: out std_logic;
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clk32: out std_logic;
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pclock: out std_logic);
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end component;
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component system is
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port (
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clk_cpu: in STD_LOGIC;
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clk_vdp: in STD_LOGIC;
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ram_we_n: out STD_LOGIC;
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ram_a: out STD_LOGIC_VECTOR(18 downto 0);
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ram_d: inout STD_LOGIC_VECTOR(7 downto 0);
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j1_up: in STD_LOGIC;
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j1_down: in STD_LOGIC;
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j1_left: in STD_LOGIC;
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j1_right: in STD_LOGIC;
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j1_tl: in STD_LOGIC;
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j1_tr: inout STD_LOGIC;
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j2_up: in STD_LOGIC;
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j2_down: in STD_LOGIC;
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j2_left: in STD_LOGIC;
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j2_right: in STD_LOGIC;
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j2_tl: in STD_LOGIC;
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j2_tr: inout STD_LOGIC;
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reset: in STD_LOGIC;
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-- pause: in STD_LOGIC;
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x: in UNSIGNED(8 downto 0);
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y: in UNSIGNED(7 downto 0);
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-- vblank: in STD_LOGIC;
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-- hblank: in STD_LOGIC;
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color: out STD_LOGIC_VECTOR(5 downto 0);
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audio: out STD_LOGIC;
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ps2_clk: in std_logic;
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ps2_data: in std_logic;
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scanSW: out std_logic;
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spi_do: in STD_LOGIC;
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spi_sclk: out STD_LOGIC;
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spi_di: out STD_LOGIC;
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spi_cs_n: buffer STD_LOGIC
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);
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end component;
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component rgb_video is
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port (
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clk16: in std_logic;
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clk8: in std_logic; --Q
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x: out unsigned(8 downto 0);
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y: out unsigned(7 downto 0);
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vblank: out std_logic;
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hblank: out std_logic;
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color: in std_logic_vector(5 downto 0);
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hsync: out std_logic;
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vsync: out std_logic;
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red: out std_logic_vector(2 downto 0);
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green: out std_logic_vector(2 downto 0);
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blue: out std_logic_vector(2 downto 0)
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-- ; blank: out std_logic
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);
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end component;
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signal clk_cpu: std_logic;
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signal clk16: std_logic;
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signal clk8: std_logic;
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signal clk32: std_logic;
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signal sel_pclock: std_logic;
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signal blank: std_logic;
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-- signal blankr: std_logic;
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signal x: unsigned(8 downto 0);
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signal y: unsigned(7 downto 0);
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signal vblank: std_logic;
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signal hblank: std_logic;
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signal color: std_logic_vector(5 downto 0);
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signal audio: std_logic;
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signal vga_hsync: std_logic;
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signal vga_vsync: std_logic;
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signal vga_red: std_logic_vector(2 downto 0);
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signal vga_green: std_logic_vector(2 downto 0);
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signal vga_blue: std_logic_vector(2 downto 0);
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signal vga_x: unsigned(8 downto 0);
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signal vga_y: unsigned(7 downto 0);
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signal vga_vblank: std_logic;
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signal vga_hblank: std_logic;
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signal rgb_hsync: std_logic;
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signal rgb_vsync: std_logic;
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signal rgb_red: std_logic_vector(2 downto 0);
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signal rgb_green: std_logic_vector(2 downto 0);
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signal rgb_blue: std_logic_vector(2 downto 0);
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signal rgb_x: unsigned(8 downto 0);
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signal rgb_y: unsigned(7 downto 0);
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signal rgb_vblank: std_logic;
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signal rgb_hblank: std_logic;
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signal rgb_clk: std_logic;
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signal scanSWk: std_logic;
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signal scanSW: std_logic;
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signal j2_tr: std_logic;
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signal c0, c1, c2 : std_logic_vector(9 downto 0); --hdmi
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signal poweron_reset: unsigned(7 downto 0) := "00000000";
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signal scandoubler_ctrl: std_logic_vector(1 downto 0);
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signal ram_we_n: std_logic;
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signal ram_a: std_logic_vector(18 downto 0);
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begin
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clock_inst: clock
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port map (
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clk_in => clk,
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sel_pclock => sel_pclock,
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clk_cpu => clk_cpu,
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clk16 => clk16,
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clk8 => clk8, --clk32 => open
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clk32 => clk32,
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pclock => rgb_clk);
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video_inst: rgb_video
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port map (
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clk16 => clk16,
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clk8 => clk8, --Q
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x => rgb_x,
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y => rgb_y,
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vblank => rgb_vblank,
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hblank => rgb_hblank,
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color => color,
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hsync => rgb_hsync,
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vsync => rgb_vsync,
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red => rgb_red,
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green => rgb_green,
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blue => rgb_blue
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-- ,blank => blankr
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);
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video_vga_inst: entity work.vga_video --vga
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port map (
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clk16 => clk16,
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x => vga_x,
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y => vga_y,
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vblank => vga_vblank,
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hblank => vga_hblank,
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color => color,
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hsync => vga_hsync,
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vsync => vga_vsync,
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red => vga_red,
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green => vga_green,
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blue => vga_blue,
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blank => blank
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);
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system_inst: system
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port map (
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clk_cpu => clk_cpu, --clk_cpu
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clk_vdp => rgb_clk, --clk8 = rgb --clk16 = vga
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ram_we_n => ram_we_n,
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ram_a => ram_a,
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ram_d => ram_d,
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j1_up => j1_up,
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j1_down => j1_down,
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j1_left => j1_left,
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j1_right => j1_right,
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j1_tl => j1_tl,
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j1_tr => j1_tr,
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j2_up => '1',
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j2_down => '1',
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j2_left => '1',
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j2_right => '1',
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j2_tl => '1',
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j2_tr => j2_tr,
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reset => '1',
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-- pause => '1',
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x => x,
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y => y,
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-- vblank => vblank,
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-- hblank => hblank,
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color => color,
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audio => audio,
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ps2_clk => ps2_clk,
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ps2_data => ps2_data,
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scanSW => scanSWk,
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spi_do => spi_do,
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spi_sclk => spi_sclk,
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spi_di => spi_di,
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spi_cs_n => spi_cs_n
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);
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dred <= red;
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dgreen <= green;
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dblue <= blue;
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dhsync <= hsync;
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dvsync <= vsync;
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led <= not spi_cs_n; --Q
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-- led <= scandoubler_ctrl(0); --debug scandblctrl reg.
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audio_l <= audio;
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audio_r <= audio;
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NTSC <= '0';
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PAL <= '1';
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---- scandlbctrl register detection for video mode initialization at start ----
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process (clk_cpu)
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begin
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if rising_edge(clk_cpu) then
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if (poweron_reset < 126) then
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scandoubler_ctrl <= ram_d(1 downto 0);
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end if;
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if poweron_reset < 254 then
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poweron_reset <= poweron_reset + 1;
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end if;
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end if;
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end process;
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sram_a <= "0001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
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sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
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-------------------------------------------------------------------------------
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vsync <= vga_vsync when scanSW='1' else '1';
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hsync <= vga_hsync when scanSW='1' else rgb_hsync;
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red <= vga_red when scanSW='1' else rgb_red;
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green <= vga_green when scanSW='1' else rgb_green;
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blue <= vga_blue when scanSW='1' else rgb_blue;
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-- vblank <= vga_vblank when scanSW='1' else rgb_vblank;
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-- hblank <= vga_hblank when scanSW='1' else rgb_hblank;
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x <= vga_x when scanSW='1' else rgb_x;
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y <= vga_y when scanSW='1' else rgb_y;
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sel_pclock <= '1' when scanSW='1' else '0';
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-- scanSW <= '1' when scanSWk = '1' else '0';
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scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
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end Behavioral;
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