mirror of https://github.com/zxdos/zxuno.git
59 lines
3.9 KiB
XML
59 lines
3.9 KiB
XML
<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pn" timeStamp="Tue Dec 09 13:36:54 2014">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="45174291E9A04A838B31B9E73C842F3B" type="project"/>
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<property name="ProjectIteration" value="5" type="project"/>
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<property name="ProjectFile" value="A:/zxuno/cores/spectrum_v2_spartan6/test14/zxuno.xise" type="project"/>
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<property name="ProjectCreationTimestamp" value="2014-02-16T16:54:30" type="project"/>
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</section>
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<section name="Project Statistics" visible="true">
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<property name="PROPEXT_MapGlobalOptimization_spartan6" value="Speed" type="process"/>
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<property name="PROP_Enable_Message_Filtering" value="true" type="design"/>
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<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
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<property name="PROP_ISimsUseCustomWaveConfigFile_behav" value="true" type="process"/>
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<property name="PROP_ImpactProjectFile" value="changed" type="process"/>
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<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
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<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
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<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
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<property name="PROP_MapLogicOptimization_spartan6" value="true" type="process"/>
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<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
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<property name="PROP_SelectedInstanceHierarchicalPath" value="/tb_ula" type="process"/>
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<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
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<property name="PROP_SynthOptEffort" value="High" type="process"/>
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<property name="PROP_SynthResSharing" value="false" type="process"/>
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<property name="PROP_SynthTopFile" value="changed" type="process"/>
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<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
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<property name="PROP_UseSmartGuide" value="false" type="design"/>
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<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
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<property name="PROP_intProjectCreationTimestamp" value="2014-02-16T16:54:30" type="design"/>
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<property name="PROP_intWbtProjectID" value="45174291E9A04A838B31B9E73C842F3B" type="design"/>
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<property name="PROP_intWbtProjectIteration" value="5" type="process"/>
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<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
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<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
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<property name="PROP_selectedSimRootSourceNode_behav" value="work.tb_ula" type="process"/>
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<property name="PROP_xilxMapCoverMode" value="Speed" type="process"/>
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<property name="PROPEXT_mapTimingMode_spartan6" value="Non Timing Driven" type="process"/>
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<property name="PROP_AutoTop" value="false" type="design"/>
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<property name="PROP_CompxlibEdkSimLib" value="false" type="process"/>
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<property name="PROP_DevFamily" value="Spartan6" type="design"/>
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<property name="PROP_ISimsUseCustomWaveConfigFilename_behav" value="changed" type="process"/>
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<property name="PROP_MapExtraEffort_spartan6" value="Normal" type="process"/>
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<property name="PROP_xilxMapEnableMultiThreading" value="2" type="process"/>
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<property name="PROP_DevDevice" value="xc6slx9" type="design"/>
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<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
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<property name="PROP_ISimSimulationRunTime_behav_tb" value="9999us" type="process"/>
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<property name="PROP_DevPackage" value="tqg144" type="design"/>
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<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
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<property name="PROP_DevSpeed" value="-3" type="design"/>
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<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
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<property name="FILE_UCF" value="1" type="source"/>
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<property name="FILE_VERILOG" value="19" type="source"/>
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<property name="FILE_VHDL" value="9" type="source"/>
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</section>
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</application>
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</document>
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