mirror of https://github.com/zxdos/zxuno.git
65 lines
2.2 KiB
Verilog
65 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 18:22:21 2015-06-07 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module coreid (
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire regaddr_changed,
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output reg [7:0] dout,
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output wire oe
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);
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`include "config.vh"
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reg [7:0] text[0:15];
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integer i;
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initial begin
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for (i=0;i<16;i=i+1) begin :gencoreid
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text[i] = COREID_STRING[(16-i)*8-1 -:8];
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end
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end
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reg [3:0] textindx = 4'h0;
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reg reading = 1'b0;
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assign oe = (zxuno_addr == IDSTRING && zxuno_regrd==1'b1);
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always @(posedge clk) begin
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if (rst_n == 1'b0 || (regaddr_changed==1'b1 && zxuno_addr==IDSTRING)) begin
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textindx <= 4'h0;
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reading <= 1'b0;
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end
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else if (oe==1'b1) begin
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reading <= 1'b1;
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end
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else if (reading == 1'b1 && oe==1'b0) begin
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reading <= 1'b0;
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textindx <= textindx + 1;
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end
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dout <= text[textindx];
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end
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endmodule
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