mirror of https://github.com/zxdos/zxuno.git
137 lines
3.9 KiB
Verilog
137 lines
3.9 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 00:44:29 2017-03-07 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module cpu_and_dma (
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input wire reset_n,
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input wire clk,
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input wire clkcpuen,
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input wire clk28en,
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input wire wait_n,
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input wire int_n,
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input wire nmi_n,
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output wire m1_n,
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output wire mreq_n,
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output wire iorq_n,
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output wire rd_n,
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output wire wr_n,
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output wire rfsh_n,
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output wire halt_n,
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output wire busak_salida_n,
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output wire [15:0] A,
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input wire [7:0] di,
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output wire [7:0] dout,
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// DMA Control signals
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input wire [7:0] zxuno_addr,
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input wire regaddr_changed,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] dmadevicedin,
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output wire [7:0] dmadevicedout,
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output wire oe
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);
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`include "config.vh"
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wire [15:0] dma_a, cpu_a;
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wire [7:0] dma_dout, cpu_dout;
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wire dma_mreq_n, dma_iorq_n, dma_rd_n, dma_wr_n;
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wire cpu_mreq_n, cpu_iorq_n, cpu_rd_n, cpu_wr_n, cpu_m1_n;
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wire busrq_n, busak_n;
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// assign mreq_n = cpu_mreq_n;
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// assign iorq_n = cpu_iorq_n;
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// assign rd_n = cpu_rd_n;
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// assign wr_n = cpu_wr_n;
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// assign m1_n = cpu_m1_n;
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// assign A = cpu_a;
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// assign dout = cpu_dout;
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assign mreq_n = (busak_n == 1'b1)? cpu_mreq_n : dma_mreq_n;
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assign iorq_n = (busak_n == 1'b1)? cpu_iorq_n : dma_iorq_n;
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assign rd_n = (busak_n == 1'b1)? cpu_rd_n : dma_rd_n;
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assign wr_n = (busak_n == 1'b1)? cpu_wr_n : dma_wr_n;
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assign m1_n = (busak_n == 1'b1)? cpu_m1_n : 1'b1;
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assign A = (busak_n == 1'b1)? cpu_a : dma_a;
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assign dout = (busak_n == 1'b1)? cpu_dout : dma_dout;
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assign busak_salida_n = busak_n;
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`ifdef ZXUNO_DMA_SUPPORT
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dma la_dma (
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.clk(clk),
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.rst_n(reset_n),
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.zxuno_addr(zxuno_addr),
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.regaddr_changed(regaddr_changed),
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.zxuno_regrd(zxuno_regrd),
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.zxuno_regwr(zxuno_regwr),
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.din(dmadevicedin),
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.dout(dmadevicedout),
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.oe(oe),
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//---- DMA bus -----
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.m1_n(m1_n),
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.busrq_n(busrq_n),
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.busak_n(busak_n),
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.dma_a(dma_a),
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.dma_din(di),
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.dma_dout(dma_dout),
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.dma_mreq_n(dma_mreq_n),
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.dma_iorq_n(dma_iorq_n),
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.dma_rd_n(dma_rd_n),
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.dma_wr_n(dma_wr_n)
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);
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`else
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assign busrq_n = 1'b1;
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assign oe = 1'b0;
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assign dma_dout = 8'h00;
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assign dma_a = 16'h0000;
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assign dma_mreq_n = 1'b1;
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assign dma_iorq_n = 1'b1;
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assign dma_rd_n = 1'b1;
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assign dma_wr_n = 1'b1;
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`endif
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tv80n_wrapper el_z80 (
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.m1_n(cpu_m1_n),
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.mreq_n(cpu_mreq_n),
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.iorq_n(cpu_iorq_n),
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.rd_n(cpu_rd_n),
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.wr_n(cpu_wr_n),
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.rfsh_n(rfsh_n),
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.halt_n(halt_n),
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.busak_n(busak_n),
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.A(cpu_a),
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.dout(cpu_dout),
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.reset_n(reset_n),
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.clk(clk),
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.clk_enable(clkcpuen),
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.wait_n(wait_n),
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.int_n(int_n),
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.nmi_n(nmi_n),
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.busrq_n(busrq_n),
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.di(di)
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);
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endmodule
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