mirror of https://github.com/zxdos/zxuno.git
48 lines
1.6 KiB
Verilog
48 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 03:40:28 2014-02-17 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module lut (
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input wire clk,
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input wire load,
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input wire [7:0] din,
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input wire [5:0] a1,
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input wire [5:0] a2,
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input wire [5:0] a3,
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output wire [7:0] do1,
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output wire [7:0] do2,
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output wire [7:0] do3
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);
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reg [7:0] lut[0:63];
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assign do1 = lut[a1];
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assign do2 = lut[a2];
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assign do3 = lut[a3];
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always @(posedge clk) begin
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if (load == 1'b1)
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lut[a3] <= din;
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end
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endmodule
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