mirror of https://github.com/zxdos/zxuno.git
72 lines
1.6 KiB
Verilog
72 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:09:00 17/01/2021
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// Design Name:
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// Module Name: monochrome
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File modified by Fernando Mosquera
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module monochrome (
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input wire [1:0] monochrome_selection,
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input wire [5:0] ri,
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input wire [5:0] gi,
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input wire [5:0] bi,
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output reg [5:0] ro,
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output reg [5:0] go,
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output reg [5:0] bo
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);
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// Escala monocromatica especifica para la paleta original
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// de Spectrum.
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wire [9:0] r_in, g_in, b_in;
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wire [9:0] y_out;
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assign r_in = {ri,ri[5:3],1'b0};
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assign g_in = {gi,gi[5:3],1'b0};
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assign b_in = {bi,bi[5:3],1'b0};
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// Equivale a la formula y=0.299r+0.587g+0.114b;
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assign y_out = (r_in>>2)+(r_in>>5)+(g_in>>1)+(g_in>>4)+(b_in>>4)+(b_in>>4);
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always @(*)
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begin
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case (monochrome_selection)
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2'b00 : begin // color
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ro = ri;
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go = gi;
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bo = bi;
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end
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2'b01 : begin // gray
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ro = y_out[9:4];
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go = y_out[9:4];
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bo = y_out[9:4];
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end
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2'b10 : begin // orange
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ro = y_out[9:4];
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go = {2'b00,y_out[9:6]};
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bo = {4'b0000,y_out[9:8]};
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end
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2'b11 : begin //green
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ro = 6'b000000;
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go = y_out[9:4];
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bo = 6'b000000;
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end
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endcase
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end
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endmodule |