mirror of https://github.com/zxdos/zxuno.git
286 lines
10 KiB
Verilog
286 lines
10 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 20:16:31 2014-12-26 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module ps2_port (
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input wire clk, // se recomienda 1 MHz <= clk <= 600 MHz
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input wire enable_rcv, // habilitar la maquina de estados de recepcion
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input wire kb_or_mouse, // 0: kb, 1: mouse
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input wire ps2clk_ext,
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input wire ps2data_ext,
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output wire kb_interrupt, // a 1 durante 1 clk para indicar nueva tecla recibida
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output reg [7:0] scancode, // make o breakcode de la tecla
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output wire released, // soltada=1, pulsada=0
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output wire extended // extendida=1, no extendida=0
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);
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localparam RCVSTART = 2'b00,
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RCVDATA = 2'b01,
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RCVPARITY = 2'b10,
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RCVSTOP = 2'b11;
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reg [7:0] key = 8'h00;
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// Fase de sincronizacion de señales externas con el reloj del sistema
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reg [1:0] ps2clk_synchr;
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reg [1:0] ps2dat_synchr;
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wire ps2clk = ps2clk_synchr[1];
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wire ps2data = ps2dat_synchr[1];
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always @(posedge clk) begin
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ps2clk_synchr[0] <= ps2clk_ext;
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ps2clk_synchr[1] <= ps2clk_synchr[0];
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ps2dat_synchr[0] <= ps2data_ext;
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ps2dat_synchr[1] <= ps2dat_synchr[0];
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end
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// De-glitcher. Sólo detecto flanco de bajada
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reg [15:0] negedgedetect = 16'h0000;
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always @(posedge clk) begin
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negedgedetect <= {negedgedetect[14:0], ps2clk};
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end
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wire ps2clkedge = (negedgedetect == 16'hF000)? 1'b1 : 1'b0;
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// Paridad instantánea de los bits recibidos
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wire paritycalculated = ^key;
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// Contador de time-out. Al llegar a 16777216 ciclos sin que ocurra
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// un flanco de bajada en PS2CLK, volvemos al estado inicial
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reg [23:0] timeoutcnt = 24'h000000;
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reg [1:0] state = RCVSTART;
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reg [1:0] regextended = 2'b00;
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reg [1:0] regreleased = 2'b00;
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reg rkb_interrupt = 1'b0;
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assign released = regreleased[1];
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assign extended = regextended[1];
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assign kb_interrupt = rkb_interrupt;
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always @(posedge clk) begin
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if (rkb_interrupt == 1'b1) begin
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rkb_interrupt <= 1'b0;
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end
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if (ps2clkedge && enable_rcv) begin
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timeoutcnt <= 24'h000000;
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case (state)
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RCVSTART: begin
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if (ps2data == 1'b0) begin
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state <= RCVDATA;
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key <= 8'h80;
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end
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end
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RCVDATA: begin
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key <= {ps2data, key[7:1]};
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if (key[0] == 1'b1) begin
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state <= RCVPARITY;
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end
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end
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RCVPARITY: begin
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if (ps2data^paritycalculated == 1'b1) begin
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state <= RCVSTOP;
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end
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else begin
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state <= RCVSTART;
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end
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end
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RCVSTOP: begin
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state <= RCVSTART;
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if (ps2data == 1'b1) begin
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scancode <= key;
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if (kb_or_mouse == 1'b1) begin
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rkb_interrupt <= 1'b1; // no se requiere mirar E0 o F0
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end
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else begin
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if (key == 8'hE0) begin
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regextended <= 2'b01;
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end
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else if (key == 8'hF0) begin
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regreleased <= 2'b01;
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end
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else begin
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regextended <= {regextended[0], 1'b0};
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regreleased <= {regreleased[0], 1'b0};
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rkb_interrupt <= 1'b1;
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end
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end
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end
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end
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default: state <= RCVSTART;
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endcase
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end
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else begin
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timeoutcnt <= timeoutcnt + 24'd1;
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if (timeoutcnt == 24'hFFFFFF) begin
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state <= RCVSTART;
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end
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end
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end
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endmodule
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module ps2_host_to_kb (
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input wire clk, // calibrado para 28 MHz
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inout wire ps2clk_ext,
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inout wire ps2data_ext,
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input wire [7:0] data,
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input wire dataload,
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output wire ps2busy,
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output wire ps2error
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);
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`define PULLCLKLOW 3'b000
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`define PULLCLKDATALOW 3'b001
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`define PULLDATALOW 3'b010
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`define SENDDATA 3'b011
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`define SENDPARITY 3'b100
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`define RCVACK 3'b101
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`define RCVIDLE 3'b110
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`define SENDFINISHED 3'b111
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reg busy = 1'b0;
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reg error = 1'b0;
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assign ps2busy = busy;
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assign ps2error = error;
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// Fase de sincronizacion de señales externas con el reloj del sistema
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reg [1:0] ps2clk_synchr;
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reg [1:0] ps2dat_synchr;
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wire ps2clk = ps2clk_synchr[1];
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wire ps2data_in = ps2dat_synchr[1];
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always @(posedge clk) begin
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ps2clk_synchr[0] <= ps2clk_ext;
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ps2clk_synchr[1] <= ps2clk_synchr[0];
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ps2dat_synchr[0] <= ps2data_ext;
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ps2dat_synchr[1] <= ps2dat_synchr[0];
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end
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// De-glitcher. Sólo detecto flanco de bajada
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reg [15:0] edgedetect = 16'h0000;
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always @(posedge clk) begin
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edgedetect <= {edgedetect[14:0], ps2clk};
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end
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wire ps2clknedge = (edgedetect == 16'hF000)? 1'b1 : 1'b0;
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wire ps2clkpedge = (edgedetect == 16'h0FFF)? 1'b1 : 1'b0;
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// Contador de time-out. Al llegar a 16777216 ciclos sin que ocurra
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// un flanco de bajada en PS2CLK, volvemos al estado inicial
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reg [23:0] timeoutcnt = 24'h000000;
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reg [2:0] state = `SENDFINISHED;
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reg [7:0] shiftreg = 8'h00;
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reg [2:0] cntbits = 3'd0;
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// Dato a enviar se guarda en rdata
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reg [7:0] rdata = 8'h00;
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// Paridad instantánea de los bits a enviar
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wire paritycalculated = ~(^rdata);
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always @(posedge clk) begin
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// Carga de rdata desde el exterior
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if (dataload) begin
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rdata <= data;
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busy <= 1'b1;
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error <= 1'b0;
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timeoutcnt <= 24'h000000;
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state <= `PULLCLKLOW;
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end
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if (!ps2clknedge) begin
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timeoutcnt <= timeoutcnt + 24'd1;
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if (timeoutcnt == 24'hFFFFFF && state != `SENDFINISHED) begin
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error <= 1'b1;
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state <= `SENDFINISHED;
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end
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end
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case (state)
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`PULLCLKLOW: begin // 280000 cuentas son 10ms para 28 MHz
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if (timeoutcnt >= 24'd3360) begin
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state <= `PULLCLKDATALOW;
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timeoutcnt <= 24'h000000;
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end
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end
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`PULLCLKDATALOW: begin
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if (timeoutcnt >= 24'd280) begin
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state <= `PULLDATALOW;
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shiftreg <= rdata;
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cntbits <= 3'd0;
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timeoutcnt <= 24'h000000;
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end
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end
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`PULLDATALOW: begin
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if (ps2clknedge) begin
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state <= `SENDDATA;
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timeoutcnt <= 24'h000000;
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end
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end
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`SENDDATA: begin
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if (ps2clknedge) begin
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timeoutcnt <= 24'h000000;
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shiftreg <= {1'b0, shiftreg[7:1]};
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cntbits <= cntbits + 1;
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if (cntbits == 3'd7)
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state <= `SENDPARITY;
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end
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end
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`SENDPARITY: begin
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if (ps2clknedge) begin
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state <= `RCVIDLE;
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timeoutcnt <= 24'h000000;
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end
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end
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`RCVIDLE: begin
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if (ps2clknedge) begin
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state <= `RCVACK;
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timeoutcnt <= 24'h000000;
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end
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end
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`RCVACK: begin
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if (ps2clknedge) begin
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state <= `SENDFINISHED;
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timeoutcnt <= 24'h000000;
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end
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end
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`SENDFINISHED: begin
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busy <= 1'b0;
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timeoutcnt <= 24'h000000;
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end
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default: begin
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timeoutcnt <= timeoutcnt + 1;
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if (timeoutcnt == 24'hFFFFFF && state != `SENDFINISHED) begin
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error <= 1'b1;
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state <= `SENDFINISHED;
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end
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end
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endcase
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end
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assign ps2data_ext = (state == `PULLCLKDATALOW || state == `PULLDATALOW) ? 1'b0 :
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(state == `SENDDATA && shiftreg[0] == 1'b0) ? 1'b0 :
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(state == `SENDPARITY && paritycalculated == 1'b0) ? 1'b0 : // si lo que se va a enviar es un 1
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1'bZ; // no se manda, sino que se pone la línea a alta impedancia
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assign ps2clk_ext = (state == `PULLCLKLOW || state == `PULLCLKDATALOW) ? 1'b0 :
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1'bZ;
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endmodule
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