mirror of https://github.com/zxdos/zxuno.git
114 lines
3.8 KiB
Verilog
114 lines
3.8 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 01:22:53 2015-06-15 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module scandoubler_ctrl (
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input wire clk,
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input wire [15:0] a,
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input wire kbd_change_video_output,
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input wire kbd_turbo_boost,
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input wire turbo_boost_allowed,
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input wire iorq_n,
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input wire rd_n,
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input wire wr_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output reg oe,
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output wire vga_enable,
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output wire scanlines_enable,
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output wire [2:0] freq_option,
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output reg [3:0] cpu_speed,
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output wire csync_option
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);
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`include "config.vh"
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reg [3:0] cpu_speed_reg = 4'b0000;
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reg [7:0] scandblctrl = INITIAL_VIDEO_VALUE;
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reg kbd_change_video_edge_detect = 1'b0;
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reg kbd_turbo_boost_edge_detect = 1'b0;
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reg ff_toggle_turbo = 1'b0;
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`ifdef VGA_OUTPUT_OPTION
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assign vga_enable = scandblctrl[0];
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assign scanlines_enable = scandblctrl[1];
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`else
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assign vga_enable = 1'b0;
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assign scanlines_enable = 1'b0;
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`endif
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assign freq_option = scandblctrl[4:2];
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assign csync_option = scandblctrl[5];
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always @* begin
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oe = 1'b0;
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dout = 8'hFF;
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if (ff_toggle_turbo == 1'b1)
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cpu_speed = 4'b0011;
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else
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cpu_speed = cpu_speed_reg;
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if (zxuno_addr == SCANDBLCTRL && zxuno_regrd == 1'b1) begin
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oe = 1'b1;
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if (ff_toggle_turbo == 1'b1)
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dout = {2'b11, scandblctrl[5:0]};
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else
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dout = scandblctrl;
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end
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else if (iorq_n == 1'b0 && rd_n == 1'b0 && a == PRISMSPEEDCTRL) begin
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oe = 1'b1;
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if (ff_toggle_turbo == 1'b1)
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dout = 8'b00000011;
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else
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dout = {4'b0000, cpu_speed_reg};
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end
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end
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always @(posedge clk) begin
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kbd_change_video_edge_detect <= kbd_change_video_output;
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if (turbo_boost_allowed == 1'b1) begin
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kbd_turbo_boost_edge_detect <= kbd_turbo_boost;
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if (kbd_turbo_boost_edge_detect == 1'b0 && kbd_turbo_boost == 1'b1)
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ff_toggle_turbo <= 1'b1;
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else if (kbd_turbo_boost_edge_detect == 1'b1 && kbd_turbo_boost == 1'b0)
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ff_toggle_turbo <= 1'b0;
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end
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if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1) begin
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scandblctrl <= din;
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cpu_speed_reg <= {4'b00, din[7:6]};
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end
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else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL && din[7:4] == 4'b0000) begin
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scandblctrl <= {din[1:0], scandblctrl[5:0]};
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cpu_speed_reg <= din[3:0];
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end
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else if (kbd_change_video_edge_detect == 1'b0 && kbd_change_video_output == 1'b1)
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scandblctrl <= {scandblctrl[7:5], ((scandblctrl[0] == 1'b0)? 3'b111 : 3'b000), scandblctrl[1], ~scandblctrl[0]};
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end
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endmodule
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