mirror of https://github.com/zxdos/zxuno.git
123 lines
2.3 KiB
Verilog
123 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:33:22 07/15/2020
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// Design Name: tv80n_wrapper
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// Module Name: D:/Users/rodriguj/Documents/zxspectrum/zxuno/repositorio/team/zxdosplus/exp27/sim/tb_cpu.v
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// Project Name: zxdos_lx25
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: tv80n_wrapper
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tb_cpu;
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// Inputs
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reg reset_n;
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reg clk;
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reg clk_enable;
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reg wait_n;
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reg int_n;
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reg nmi_n;
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reg busrq_n;
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reg [7:0] di;
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// Outputs
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wire m1_n;
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wire mreq_n;
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wire iorq_n;
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wire rd_n;
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wire wr_n;
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wire rfsh_n;
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wire halt_n;
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wire busak_n;
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wire [15:0] A;
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wire [7:0] dout;
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// Instantiate the Unit Under Test (UUT)
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tv80n_wrapper uut (
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.m1_n(m1_n),
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.mreq_n(mreq_n),
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.iorq_n(iorq_n),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.rfsh_n(rfsh_n),
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.halt_n(halt_n),
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.busak_n(busak_n),
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.A(A),
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.dout(dout),
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.reset_n(reset_n),
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.clk(clk),
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.clk_enable(clk_enable),
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.wait_n(wait_n),
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.int_n(int_n),
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.nmi_n(nmi_n),
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.busrq_n(busrq_n),
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.di(di)
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);
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reg [7:0] mem[0:15];
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initial begin
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mem[ 0] = 8'h21;
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mem[ 1] = 8'h0F;
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mem[ 2] = 8'h00;
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mem[ 3] = 8'h36;
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mem[ 4] = 8'h00;
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mem[ 5] = 8'h34;
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mem[ 6] = 8'd211;
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mem[ 7] = 8'hFE;
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mem[ 8] = 8'h18;
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mem[ 9] = 8'd251;
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mem[10] = 8'h00;
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mem[11] = 8'h00;
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mem[12] = 8'h00;
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mem[13] = 8'h00;
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mem[14] = 8'h00;
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mem[15] = 8'h00;
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end
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always @* begin
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if (mreq_n == 1'b0 && rd_n == 1'b0)
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di = #10 mem[A];
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if (mreq_n == 1'b0 && wr_n == 1'b0)
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mem[A] = #5 dout;
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end
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initial begin
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// Initialize Inputs
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reset_n = 0;
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clk = 0;
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clk_enable = 1;
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wait_n = 1;
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int_n = 1;
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nmi_n = 1;
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busrq_n = 1;
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repeat (3)
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@(posedge clk);
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reset_n = 1;
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// Add stimulus here
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repeat (256)
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@(posedge clk);
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$finish;
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end
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always begin
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clk = #(1000/56) ~clk;
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end
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endmodule
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