more work on init and reorganizing

Former-commit-id: d0d9f5ffc49202c9b2bb9eb9e714f94b61ce7027 [formerly f0e9845831b2bfa2a3caff4190a364d5a7c1a392] Former-commit-id: 65e8898e08e9a837feb6d8178e2e85521c8e8c82
2017-05-10 12:57:45 -05:00 · 2017-05-10 12:57:45 -05:00 · c40657c8ab
parent 3e899cf712
commit c40657c8ab
12 changed files with 37 additions and 14 deletions
--- a/disassembly/GE007.rom.asm
+++ b/disassembly/GE007.rom.asm
@ -2,11 +2,12 @@ arch n64.cpu
 endian msb
 output "GE007.n64", create
 include "lib/N64.INC"
+include "lib/GE007.inc"
 define romsize($C00000)
 fill {romsize}, $FF
 origin $00000000;rom_file_start:;rom_start:
-include "code/bss.asm"
-include "code/stack.asm"
+include "code/bss.inc"
+include "code/stack.inc"
 include "rom/romheader.asm"
 include "code/boot.asm"
 include "rodata/rodata.rz.asm"
--- a/disassembly/GE007.sym.REMOVED.git-id
+++ b/disassembly/GE007.sym.REMOVED.git-id
@ -1 +1 @@
-efb384ef7cc4ce8e0e1a963396ea2c580d337a6e
+1491c6f3f0da1b1db10a1053d5971a5c4c99b62f
--- a/disassembly/code/boot.asm.REMOVED.git-id
+++ b/disassembly/code/boot.asm.REMOVED.git-id
@ -1 +1 @@
-48cee3ccec613860f2337c13f3fd4d5ea574514f
+65f3feacd7e469a974d0aa9702eb44ea77ffcbbe
--- a/disassembly/code/boot/entry.asm.REMOVED.git-id
+++ b/disassembly/code/boot/entry.asm.REMOVED.git-id
@ -0,0 +1 @@
+c28c4932b97bf5246080adeac71267385dcd91a1
--- a/disassembly/code/bss.inc
+++ b/disassembly/code/bss.inc
@ -7,5 +7,3 @@ mainthread:
 base $8008E360
 seg_bss_end:

-variable seg_bss_size(seg_bss_end-seg_bss_start)
-
--- a/disassembly/code/stack.inc
+++ b/disassembly/code/stack.inc
@ -1,4 +1,6 @@
+
 base $80300000
+seg_sp_start:
 decompression_buffer:

 base $803AB400
@ -27,3 +29,4 @@ sp_main:

 base $803B3950
 sp_audi:
+seg_sp_end:
--- a/disassembly/code/tlb_code.asm
+++ b/disassembly/code/tlb_code.asm
@ -1,5 +1,5 @@
 base origin()
-seg_tlbcode_start:
+seg_tlbcode_rom_start:
 base $7F000000
 tlb_code_vaddr_start:

@ -7,7 +7,5 @@ insert binarytlbcode, "tlb_code.bin", (origin() - $34B30)

 tlb_code_vaddr_end:
 base origin()
-seg_tlbcode_end:
-
-variable seg_tlbcode_size(seg_tlbcode_end-seg_tlbcode_start)
+seg_tlbcode_rom_end:

--- a/disassembly/lib/GE007.inc
+++ b/disassembly/lib/GE007.inc
@ -0,0 +1,23 @@
+variable seg_boot_rom_size(seg_boot_rom_end-seg_boot_rom_start)
+variable seg_rarezip_rom_size(seg_rarezip_rom_end-seg_rarezip_rom_start)
+variable seg_bss_size(seg_bss_end-seg_bss_start)
+variable seg_tlbcode_rom_size(seg_tlbcode_rom_end-seg_tlbcode_rom_start)
+variable seg_rodata_rom_size(seg_rodata_rom_end-seg_rodata_rom_start)
+variable seg_sp_start(seg_sp_end-seg_sp_start)
+
+macro getaddresstoregister(address, reg) {
+ define return({reg}) //what register to return in
+
+ lui {return}, ({address} >> 16) //address upper
+ jr ra
+ addiu {return}, {return}, {address} //address lower
+}
+
+macro jumpaddressviaregister(address,reg) {
+ define jumptarget({reg})
+
+ lui {jumptarget},({address} >> 16)
+ addiu {jumptarget}, {jumptarget}, {address}
+ jr {jumptarget}
+}
+
--- a/disassembly/lib/N64.INC.REMOVED.git-id
+++ b/disassembly/lib/N64.INC.REMOVED.git-id
@ -1 +1 @@
-b0ad95fa205c0c1aa784b30041f7a90f771da123
+d0717f99cf7157a2e49e1a5c39f882e204f3c0bb
--- a/disassembly/rodata/rodata.rz.asm
+++ b/disassembly/rodata/rodata.rz.asm
@ -9,4 +9,3 @@ insert padding,"pad_to_33590"
 base origin()
 seg_rodata_rom_end:

-variable seg_rodata_rom_size(seg_rodata_rom_end-seg_rodata_rom_start)
--- a/disassembly/rom/romheader.asm
+++ b/disassembly/rom/romheader.asm
@ -11,7 +11,7 @@
  dw $000F // Initial Clock Rate

 // VECTOR
-  dw Start // Boot Address Offset
+  dw boot.start // Boot Address Offset
  dw $1447 // Release Offset

 // COMPLEMENT CHECK & CHECKSUM
--- a/filelist.txt.REMOVED.git-id
+++ b/filelist.txt.REMOVED.git-id
@ -1 +1 @@
-8a23c376ea2f7fe11669c1f441981a12312608ff
+81e47060288a3a1f1030a178a0cf8e75acc09ecb