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陳韋任 (Wei-Ren Chen) 357414daa4 target-mips: fix wrong microMIPS opcode encoding 
While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.

[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
    Application-Specific Extension to the microMIPS32 Architecture

Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 6801038bc5)

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
 		2012-11-30 16:07:16 -06:00
..
Makefile.objs target-mips: switch to AREG0 free mode 2012-10-09 01:42:08 -05:00
TODO Replace Qemu by QEMU in internal documentation 2012-04-07 13:58:25 +00:00
cpu-qom.h target-mips: QOM'ify CPU 2012-04-30 11:32:13 +02:00
cpu.c target-mips: Start QOM'ifying CPU init 2012-04-30 11:32:13 +02:00
cpu.h MIPS/user: Fix reset CPU state initialization 2012-10-09 01:58:30 -05:00
helper.c target-mips: Use cpu_reset() in do_interrupt() 2012-06-04 23:00:43 +02:00
helper.h target-mips: switch to AREG0 free mode 2012-10-09 01:42:08 -05:00
machine.c target-mips: Don't overuse CPUState 2012-03-14 22:20:25 +01:00
mips-defs.h
…
op_helper.c MIPS/user: Fix reset CPU state initialization 2012-10-09 01:58:30 -05:00
translate.c target-mips: fix wrong microMIPS opcode encoding 2012-11-30 16:07:16 -06:00
translate_init.c mips: Default to using one VPE and one TC. 2011-09-06 11:09:39 +02:00