mirror of https://github.com/zxdos/zxuno.git
Añado archivos Quest para sms test4
This commit is contained in:
antoniovillena
parent
99cc4a8f67
commit
39a686cf82
File diff suppressed because it is too large
Load Diff
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@ -17,6 +17,7 @@ const fat_t *fat = 0xc010;
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const UBYTE *fat_buffer = 0xc100;
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const UBYTE *data_buffer = 0xc300;
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const file_descr_t *directory_buffer= 0xc500;
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//const BYTE *card_type = 0xc700; //q
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void fat_init32();
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void fat_init16();
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@ -38,38 +39,57 @@ WORD load_word(UBYTE *ptr)
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int fat_init()
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{
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DWORD sector;
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UBYTE hasMBR;
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sector = 0;
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if (!sd_load_sector(data_buffer, sector)) {
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console_puts("Error loading MBR\n");
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console_puts("Error loading Sector 0\n");
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return FALSE;
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}
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if ((data_buffer[0x1fe]!=0x55) || (data_buffer[0x1ff]!=0xaa)) {
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console_puts("Wrong MBR\n");
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console_puts("Wrong Sector 0\n");
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return FALSE;
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}
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//console_print_byte(data_buffer[0x1fe]); //q
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//console_print_byte(data_buffer[0x1ff]); //q
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switch (data_buffer[0x1c2]) {
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case 0x06:
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case 0x04:
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fat->fat32 = FALSE;
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hasMBR = TRUE;
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break;
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case 0x0b:
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case 0x0c:
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fat->fat32 = TRUE;
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hasMBR = TRUE;
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break;
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default:
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console_puts("Unsupported FileSystem (FAT16/32 only)\n");
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return FALSE;
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if (data_buffer[0x55]==0x33) { //check possible FAT type when NO MBR found (32)
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fat->fat32 = TRUE;
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hasMBR = FALSE;
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} else if (data_buffer[0x39]==0x31) { //check possible FAT type when NO MBR found (16)
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fat->fat32 = FALSE;
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hasMBR = FALSE;
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} else {
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console_puts("Unsupported FileSystem (FAT16/32 only)\n");
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return FALSE;
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}
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}
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sector = load_dword(&data_buffer[0x1c6]);
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if (hasMBR)
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sector = load_dword(&data_buffer[0x1c6]);
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else
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sector = 0;
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//sector = 0x800;
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#ifdef DEBUG_FAT
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debug_puts("first sector: ");
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debug_print_dword(sector);
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debug_puts("\n");
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#endif
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//console_print_dword(sector); //q
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if (!sd_load_sector(data_buffer, sector)) {
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console_puts("Error while loading boot sector\n");
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@ -78,6 +98,14 @@ int fat_init()
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if ((data_buffer[0x1fe]!=0x55) || (data_buffer[0x1ff]!=0xaa)) {
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console_puts("Wrong boot record\n");
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//console_print_byte(data_buffer[0x1fe]); //q
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//console_print_byte(data_buffer[0x1ff]); //q
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//console_print_byte(data_buffer[0]);
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//console_print_byte(data_buffer[1]);
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//console_print_byte(data_buffer[2]);
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//console_print_byte(data_buffer[3]);
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//console_print_byte(data_buffer[4]);
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//console_print_byte(data_buffer[5]);
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return FALSE;
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}
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@ -48,6 +48,12 @@ void main()
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vdp_set_address(0x3f00);
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vdp_write(0xd0);
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//Sound off - if resetted from a prior game
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set_sound_volume(0,0);
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set_sound_volume(1,0);
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set_sound_volume(2,0);
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set_sound_volume(3,0);
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while (1) {
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console_init();
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console_clear();
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@ -56,6 +62,7 @@ void main()
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console_puts("MASTER SYSTEM ROM LOADER\n");
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console_gotoxy(3,1);
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console_puts("------------------------\n");
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//console_gotoxy(3,3);
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i = 0;
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if (!sd_init()) {
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@ -66,6 +73,7 @@ void main()
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#endif
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if (!fat_init()) {
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//console_puts("could not initialize FAT system\n"); //qq
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} else {
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#ifdef DEBUG2
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console_puts("FAT system initialized\n");
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@ -84,10 +92,13 @@ void choose_mode(int sd_ok)
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int i = 0;
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console_gotoxy(9,10);
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if (sd_ok) {
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//console_puts("load from SD card");
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pick_and_load_rom();
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} else {
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console_puts("retry SD/MMC card");
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}
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//console_gotoxy(9,12);
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//console_puts("boot SRAM");
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for (;;) {
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int key;
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@ -100,6 +111,9 @@ void choose_mode(int sd_ok)
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case JOY_UP:
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i = 0;
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break;
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// case JOY_DOWN:
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// i = 1;
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// break;
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case JOY_FIREA:
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case JOY_FIREB:
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if (i==0) {
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@ -131,7 +145,10 @@ void pick_and_load_rom()
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for (;;) {
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int key;
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print_dir(top_of_screen,current);
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//key = wait_key();
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key = read_joypad1();
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//switch (key) {
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//case JOY_UP:
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cont++;
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if (cont>20)
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cdiv= 3;
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@ -144,8 +161,9 @@ void pick_and_load_rom()
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}
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}
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cont = 0;
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}
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} //break;
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if ((key & JOY_DOWN) && (cont%cdiv==0)) {
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//case JOY_DOWN:
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if (current[1].type!=0) {
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current++;
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cdiv = 8;
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@ -154,7 +172,8 @@ void pick_and_load_rom()
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}
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}
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cont = 0;
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}
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} //break;
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//case JOY_LEFT:
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if ((key & JOY_LEFT) && (cont%(cdiv)==0)) {
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if ((current!=entries) && current>(entries+4)) {
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current = current-5;
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@ -167,7 +186,8 @@ void pick_and_load_rom()
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top_of_screen = current;
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}
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cont = 0;
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}
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} //break;
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//case JOY_RIGHT:
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if ((key & JOY_RIGHT) && (cont%(cdiv)==0)) {
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if (current[5].type!=0 && current[4].type!=0 && current[3].type!=0 && current[2].type!=0 && current[1].type!=0) {
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current = current + 5;
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@ -187,10 +207,13 @@ void pick_and_load_rom()
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current = current+3;
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else if (current[5].type == 0)
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current = current+4;
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//top_of_screen = current;
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cdiv = 8;
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}
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cont = 0;
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}
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} //break;
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//case JOY_FIREA:
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//case JOY_FIREB:
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if ((key & (JOY_FIREA | JOY_FIREB)) && (cont%cdiv==0)) {
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if ((current->type&0x10)==0) {
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entries = fat_open_directory(current->cluster);
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@ -207,7 +230,8 @@ void pick_and_load_rom()
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return;
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}
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cont = 0;
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}
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} //break;
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//}
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}
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}
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@ -1,8 +1,8 @@
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SET machine=sms_rgb
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SET ruta_ucf=src\sms_rgb
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SET machine=sms
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SET ruta_ucf=src\sms
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SET ruta_bat=..\
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call %ruta_bat%genxst.bat
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call %ruta_bat%generar.bat v2
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call %ruta_bat%generar.bat v3
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rem call %ruta_bat%generar.bat v2
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rem call %ruta_bat%generar.bat v3
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call %ruta_bat%generar.bat v4
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call %ruta_bat%generar.bat Ap
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rem call %ruta_bat%generar.bat Ap
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@ -3,6 +3,7 @@ vhdl work "T80/T80_Reg.vhd"
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vhdl work "T80/T80_Pack.vhd"
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vhdl work "T80/T80_MCode.vhd"
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vhdl work "T80/T80_ALU.vhd"
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vhdl work "src/vdp_vram_fill.vhd"
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vhdl work "src/vdp_sprites.vhd"
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vhdl work "src/vdp_background.vhd"
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vhdl work "T80/T80.vhd"
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@ -11,15 +12,20 @@ vhdl work "src/vdp_main.vhd"
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vhdl work "src/vdp_cram.vhd"
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vhdl work "src/psg_tone.vhd"
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vhdl work "src/psg_noise.vhd"
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vhdl work "src/keyb/ps2_intf.vhd"
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vhdl work "src/dac.vhd"
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vhdl work "T80/T80se.vhd"
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vhdl work "src/vdp.vhd"
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vhdl work "src/spi.vhd"
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vhdl work "src/ram.vhd"
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vhdl work "src/psg.vhd"
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verilog work "src/multiboot_v4.v"
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vhdl work "src/keyb/keyboard.vhd"
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vhdl work "src/io.vhd"
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vhdl work "src/bootloader_rom.vhd"
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vhdl work "src/bootrom_fill.vhd"
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vhdl work "src/vga_video.vhd"
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vhdl work "src/system.vhd"
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vhdl work "src/rgb_video.vhd"
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vhdl work "src/dvi-d/dvid.vhd"
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vhdl work "src/clocks.vhd"
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vhdl work "src/sms_rgb.vhd"
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vhdl work "src/sms.vhd"
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@ -1,9 +1,10 @@
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-w
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-g Binary:no
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-g DebugBitstream:No
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-g Compress
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-g Binary:no
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-g CRC:Enable
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-g Reset_on_err:No
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-g ConfigRate:4
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-g ConfigRate:2
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-g ProgPin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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@ -1,15 +1,15 @@
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set -tmpdir "projnav.tmp"
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set -xsthdpdir "xst"
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run
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-ifn sms_rgb.prj
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-ofn sms_rgb
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-ifn sms.prj
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-ofn sms
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-ofmt NGC
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-p xc6slx9-3-tqg144
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-top sms_rgb
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-top sms
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-iuc YES
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-keep_hierarchy No
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-netlist_hierarchy As_Optimized
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-rtlview Yes
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@ -0,0 +1,52 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity boot_rom is
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generic (
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ADDR_WIDTH : integer := 14;
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DATA_WIDTH : integer := 8
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);
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port (
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clk : in std_logic;
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RD_n : in std_logic;
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A : in std_logic_vector(13 downto 0);
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D_out : out std_logic_vector(7 downto 0)
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);
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end;
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architecture RTL of boot_rom is
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constant MEM_DEPTH : integer := 2**ADDR_WIDTH;
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type mem_type is array (0 to MEM_DEPTH-1) of signed(DATA_WIDTH-1 downto 0);
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impure function init_mem(mif_file_name : in string) return mem_type is
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file mif_file : text open read_mode is mif_file_name;
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variable mif_line : line;
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variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
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variable temp_mem : mem_type;
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begin
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for i in mem_type'range loop
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readline(mif_file, mif_line);
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read(mif_line, temp_bv);
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temp_mem(i) := signed(to_stdlogicvector(temp_bv));
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end loop;
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return temp_mem;
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end function;
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shared variable mem : mem_type := init_mem("boot.mif");
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begin
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p_rom : process
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begin
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wait until rising_edge(clk);
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if (RD_n = '0') then --1
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D_out <= std_logic_vector(mem(to_integer(unsigned(A))));
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end if;
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end process;
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end RTL;
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@ -1,65 +1,3 @@
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-- file: clk_wiz_v1_8.vhd
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--
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-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
|
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--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- User entered comments
|
||||
------------------------------------------------------------------------------
|
||||
-- None
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
------------------------------------------------------------------------------
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||||
-- CLK_OUT1 32.024 0.000 50.0 271.037 265.971
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||||
-- CLK_OUT2 16.012 0.000 50.0 322.832 265.971
|
||||
-- CLK_OUT3 8.006 0.000 50.0 365.304 265.971
|
||||
-- CLK_OUT4 64.048 0.000 50.0 224.987 265.971
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- Input Clock Input Freq (MHz) Input Jitter (UI)
|
||||
------------------------------------------------------------------------------
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||||
|
|
@ -79,17 +17,17 @@ entity clock is
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|||
port
|
||||
(-- Clock in ports
|
||||
clk_in : in std_logic;
|
||||
sel_pclock : in std_logic;
|
||||
-- Clock out ports
|
||||
clk32 : out std_logic;
|
||||
clk8 : out std_logic;
|
||||
clk16 : out std_logic;
|
||||
clk_cpu : out std_logic;
|
||||
clk64 : out std_logic
|
||||
clk32 : out std_logic;
|
||||
pclock : out std_logic
|
||||
);
|
||||
end clock;
|
||||
|
||||
architecture behavioral of clock is
|
||||
-- attribute CORE_GENERATION_INFO : string;
|
||||
-- attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v1_8,clk_wiz_v1_8,{component_name=clk_wiz_v1_8,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
|
||||
-- Input clock buffering / unused connectors
|
||||
signal clkin1 : std_logic;
|
||||
-- Output clock buffering / unused connectors
|
||||
|
|
@ -106,7 +44,6 @@ architecture behavioral of clock is
|
|||
|
||||
begin
|
||||
|
||||
|
||||
-- Input buffering
|
||||
--------------------------------------
|
||||
clkin1_buf : IBUFG
|
||||
|
|
@ -126,19 +63,19 @@ begin
|
|||
(BANDWIDTH => "OPTIMIZED",
|
||||
CLK_FEEDBACK => "CLKFBOUT",
|
||||
COMPENSATION => "SYSTEM_SYNCHRONOUS",
|
||||
DIVCLK_DIVIDE => 2,
|
||||
CLKFBOUT_MULT => 41,
|
||||
DIVCLK_DIVIDE => 1,
|
||||
CLKFBOUT_MULT => 16,
|
||||
CLKFBOUT_PHASE => 0.000,
|
||||
CLKOUT0_DIVIDE => 128, --32 = 32Mhz, --128 = 8Mhz
|
||||
CLKOUT0_DIVIDE => 100, --25 = 32Mhz, --100 = 8Mhz
|
||||
CLKOUT0_PHASE => 0.000,
|
||||
CLKOUT0_DUTY_CYCLE => 0.500,
|
||||
CLKOUT1_DIVIDE => 64,
|
||||
CLKOUT1_DIVIDE => 50, --50 = 16MHz
|
||||
CLKOUT1_PHASE => 0.000,
|
||||
CLKOUT1_DUTY_CYCLE => 0.500,
|
||||
CLKOUT2_DIVIDE => 35, --35 ~33Mhz Z80 --128 = 8mhz --51 = 20mhz
|
||||
CLKOUT2_DIVIDE => 27, --27 ~29.5Mhz Z80 --100 = 8mhz --50 = 16mhz
|
||||
CLKOUT2_PHASE => 0.000,
|
||||
CLKOUT2_DUTY_CYCLE => 0.500,
|
||||
CLKOUT3_DIVIDE => 16,
|
||||
CLKOUT3_DIVIDE => 25, --25 = 32Mhz for HDMI clock
|
||||
CLKOUT3_PHASE => 0.000,
|
||||
CLKOUT3_DUTY_CYCLE => 0.500,
|
||||
CLKIN_PERIOD => 20.0,
|
||||
|
|
@ -168,7 +105,7 @@ begin
|
|||
|
||||
clkout1_buf : BUFG
|
||||
port map
|
||||
(O => clk32,
|
||||
(O => clk8,
|
||||
I => clkout0);
|
||||
|
||||
clkout2_buf : BUFG
|
||||
|
|
@ -183,7 +120,14 @@ begin
|
|||
|
||||
clkout4_buf : BUFG
|
||||
port map
|
||||
(O => clk64,
|
||||
(O => clk32,
|
||||
I => clkout3);
|
||||
|
||||
pclock_sel : BUFGMUX --muxer del relojes 16 / 8 para el pixel clock del scandoubler on/off
|
||||
port map
|
||||
(O => pclock,
|
||||
I0 => clkout0, --el de 8
|
||||
I1 => clkout1, --el de 16
|
||||
S => sel_pclock);
|
||||
|
||||
end behavioral;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,148 @@
|
|||
-------------------------------------------------------------------
|
||||
-- minimalDVID_encoder.vhd : A quick and dirty DVI-D implementation
|
||||
--
|
||||
-- Author: Mike Field <hamster@snap.net.nz>
|
||||
--
|
||||
-- DVI-D uses TMDS as the 'on the wire' protocol, where each 8-bit
|
||||
-- value is mapped to one or two 10-bit symbols, depending on how
|
||||
-- many 1s or 0s have been sent. This makes it a DC balanced protocol,
|
||||
-- as a correctly implemented stream will have (almost) an equal
|
||||
-- number of 1s and 0s.
|
||||
--
|
||||
-- Because of this implementation quite complex. By restricting the
|
||||
-- symbols to a subset of eight symbols, all of which having have
|
||||
-- five ones (and therefore five zeros) this complexity drops away
|
||||
-- leaving a simple implementation. Combined with a DDR register to
|
||||
-- send the symbols the complexity is kept very low.
|
||||
--
|
||||
-------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity MinimalDVID_encoder is
|
||||
Port ( clk : in STD_LOGIC;
|
||||
hsync, vsync, blank : in STD_LOGIC;
|
||||
red, green, blue : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
hdmi_p, hdmi_n : out STD_LOGIC_VECTOR (3 downto 0));
|
||||
end MinimalDVID_encoder;
|
||||
|
||||
architecture Behavioral of MinimalDVID_encoder is
|
||||
type a_symbols is array (0 to 3) of std_logic_vector(9 downto 0);
|
||||
type a_colours is array (0 to 2) of std_logic_vector(2 downto 0);
|
||||
-- type a_ctls is array (0 to 2) of std_logic_vector(1 downto 0);
|
||||
type a_output_bits is array (0 to 3) of std_logic_vector(1 downto 0);
|
||||
|
||||
signal symbols : a_symbols := (others => (others => '0'));
|
||||
signal high_speed_sr : a_symbols := (others => (others => '0'));
|
||||
signal colours : a_colours := (others => (others => '0'));
|
||||
-- signal ctls : a_ctls := (others => (others => '0'));
|
||||
signal output_bits : a_output_bits := (others => (others => '0'));
|
||||
|
||||
signal ctls: std_logic_vector(1 downto 0); --Q
|
||||
|
||||
-- Controlling when the transfers into the high speed domain occur
|
||||
signal latch_high_speed : std_logic_vector(4 downto 0) := "00001";
|
||||
|
||||
-- The signals from the DDR outputs to the output buffers
|
||||
signal serial_outputs : std_logic_vector(3 downto 0);
|
||||
|
||||
-- For generating the x5 clocks
|
||||
signal clk_x5, clk_x5_unbuffered : std_logic;
|
||||
signal clk_feedback : std_logic;
|
||||
|
||||
begin
|
||||
ctls <= vsync & hsync; -- syncs are set in the channel 0 CTL periods
|
||||
|
||||
colours(0) <= blue;
|
||||
colours(1) <= green;
|
||||
colours(2) <= red;
|
||||
|
||||
symbols(3) <= "0000011111"; -- the clock channel symbol is static
|
||||
|
||||
clk_proc: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
for i in 0 to 2 loop
|
||||
if blank = '1' then
|
||||
case ctls is
|
||||
when "00" => symbols(i) <= "1101010100";
|
||||
when "01" => symbols(i) <= "0010101011";
|
||||
when "10" => symbols(i) <= "0101010100";
|
||||
when others => symbols(i) <= "1010101011";
|
||||
end case;
|
||||
else
|
||||
case colours(i) is
|
||||
--- Colour TMDS symbol Value
|
||||
when "000" => symbols(i) <= "0111110000"; -- 0x10
|
||||
when "001" => symbols(i) <= "0001001111"; -- 0x2F
|
||||
when "010" => symbols(i) <= "0111001100"; -- 0x54
|
||||
when "011" => symbols(i) <= "0010001111"; -- 0x6F
|
||||
when "100" => symbols(i) <= "0000101111"; -- 0x8F
|
||||
when "101" => symbols(i) <= "1000111001"; -- 0xB4
|
||||
when "110" => symbols(i) <= "1000011011"; -- 0xD2
|
||||
when others => symbols(i) <= "1011110000"; -- 0xEF
|
||||
end case;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_x5)
|
||||
begin
|
||||
---------------------------------------------------------------
|
||||
-- Now take the 10-bit words and take it into the high-speed
|
||||
-- clock domain once every five cycles.
|
||||
--
|
||||
-- Then send out two bits every clock cycle using DDR output
|
||||
-- registers.
|
||||
---------------------------------------------------------------
|
||||
if rising_edge(clk_x5) then
|
||||
for i in 0 to 3 loop
|
||||
output_bits(i) <= high_speed_sr(i)(1 downto 0);
|
||||
if latch_high_speed(0) = '1' then
|
||||
high_speed_sr(i) <= symbols(i);
|
||||
else
|
||||
high_speed_sr(i) <= "00" & high_speed_sr(i)(9 downto 2);
|
||||
end if;
|
||||
end loop;
|
||||
latch_high_speed <= latch_high_speed(0) & latch_high_speed(4 downto 1);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
g1: for i in 0 to 3 generate
|
||||
--------------------------------------------------------
|
||||
-- Convert the TMDS codes into a serial stream, two bits
|
||||
-- at a time using a DDR register
|
||||
--------------------------------------------------------
|
||||
to_serial: ODDR2
|
||||
generic map(DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC")
|
||||
port map (C0 => clk_x5, C1 => not clk_x5, CE => '1', R => '0', S => '0',
|
||||
D0 => output_bits(i)(0), D1 => output_bits(i)(1), Q => serial_outputs(i));
|
||||
OBUFDS_c0 : OBUFDS port map ( O => hdmi_p(i), OB => hdmi_n(i), I => serial_outputs(i));
|
||||
end generate;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Use a PLL to generate a x5 clock, which is used to drive
|
||||
-- the DDR registers.This allows 10 bits to be sent for every
|
||||
-- pixel clock
|
||||
------------------------------------------------------------------
|
||||
PLL_BASE_inst : PLL_BASE generic map (
|
||||
CLKFBOUT_MULT => 10,
|
||||
CLKOUT0_DIVIDE => 2,
|
||||
CLKOUT0_PHASE => 0.0, -- Output 5x original frequency
|
||||
CLK_FEEDBACK => "CLKFBOUT",
|
||||
CLKIN_PERIOD => 13.33,
|
||||
DIVCLK_DIVIDE => 1
|
||||
) port map (
|
||||
CLKFBOUT => clk_feedback,
|
||||
CLKOUT0 => clk_x5_unbuffered,
|
||||
CLKFBIN => clk_feedback,
|
||||
CLKIN => clk,
|
||||
RST => '0'
|
||||
);
|
||||
|
||||
BUFG_pclkx5 : BUFG port map ( I => clk_x5_unbuffered, O => clk_x5);
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -74,7 +74,8 @@ begin
|
|||
D_out(6) <= '0';
|
||||
end if;
|
||||
D_out(5) <= '1';
|
||||
D_out(4) <= RESET;
|
||||
D_out(4) <= RESET; --Q
|
||||
-- D_out(4) <= '1';
|
||||
-- 4=j2_tr
|
||||
if ctrl(2)='0' then
|
||||
D_out(3) <= ctrl(6);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,143 @@
|
|||
-- PS/2 Keyboard
|
||||
--
|
||||
-- 2015 modified by Quest - orig: 2011 Mike Stirling
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity keyboard is
|
||||
port (
|
||||
CLOCK : in std_logic;
|
||||
PS2_CLK : in std_logic;
|
||||
PS2_DATA : in std_logic;
|
||||
resetKey : out std_logic;
|
||||
MRESET : out std_logic;
|
||||
scanSW : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture rtl of keyboard is
|
||||
|
||||
-- PS/2 interface
|
||||
component ps2_intf is
|
||||
generic (filter_length : positive := 8);
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
nRESET : in std_logic;
|
||||
|
||||
-- PS/2 interface (could be bi-dir)
|
||||
PS2_CLK : in std_logic;
|
||||
PS2_DATA : in std_logic;
|
||||
|
||||
-- Byte-wide data interface - only valid for one clock
|
||||
-- so must be latched externally if required
|
||||
DATA : out std_logic_vector(7 downto 0);
|
||||
VALID : out std_logic
|
||||
-- ;ERROR : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
-- Interface to PS/2 block
|
||||
signal keyb_data : std_logic_vector(7 downto 0);
|
||||
signal keyb_valid : std_logic;
|
||||
--signal keyb_error : std_logic;
|
||||
|
||||
-- Internal signals
|
||||
signal release : std_logic;
|
||||
--signal extended : std_logic;
|
||||
signal nRESET : std_logic;
|
||||
|
||||
-- controles
|
||||
signal CTRL : std_logic;
|
||||
signal ALT : std_logic;
|
||||
signal PAUSE: std_logic := '0';
|
||||
signal VIDEO: std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
ps2 : ps2_intf port map (
|
||||
CLOCK, nRESET,
|
||||
PS2_CLK, PS2_DATA,
|
||||
keyb_data, keyb_valid --, keyb_error
|
||||
);
|
||||
|
||||
-- Decode PS/2 data
|
||||
process(CLOCK,nRESET)
|
||||
begin
|
||||
if nRESET = '0' then
|
||||
release <= '0';
|
||||
-- extended <= '0';
|
||||
resetKey <= '0';
|
||||
|
||||
elsif rising_edge(CLOCK) then
|
||||
|
||||
if keyb_valid = '1' then
|
||||
-- Decode keyboard input
|
||||
if keyb_data = X"e0" then
|
||||
-- Extended key code follows
|
||||
-- extended <= '1';
|
||||
elsif keyb_data = X"f0" then
|
||||
-- Release code follows
|
||||
release <= '1';
|
||||
else
|
||||
-- Cancel extended/release flags for next time
|
||||
release <= '0';
|
||||
-- extended <= '0';
|
||||
|
||||
-- Decode scan codes
|
||||
case keyb_data is
|
||||
|
||||
--Master reset
|
||||
when X"66" =>
|
||||
if (CTRL = '1' and ALT = '1') then
|
||||
MRESET <= not release;
|
||||
end if;
|
||||
when X"14" => CTRL <= not release;
|
||||
when X"11" => ALT <= not release;
|
||||
|
||||
when X"07" => resetKey <= not release; -- F12 reset/menu
|
||||
|
||||
when X"75" => scanSW(0) <= not release; --up + q
|
||||
when X"15" => scanSW(0) <= not release;
|
||||
when X"72" => scanSW(1) <= not release; --down + a
|
||||
when X"1C" => scanSW(1) <= not release;
|
||||
when X"6B" => scanSW(2) <= not release; --left + o
|
||||
when X"44" => scanSW(2) <= not release;
|
||||
when X"74" => scanSW(3) <= not release; --right + p
|
||||
when X"4D" => scanSW(3) <= not release;
|
||||
when X"1A" => scanSW(4) <= not release; --bl = z, enter, space
|
||||
when X"5A" => scanSW(4) <= not release;
|
||||
when X"29" => scanSW(4) <= not release;
|
||||
when X"22" => scanSW(5) <= not release; --br = x, L-win
|
||||
when X"1F" => scanSW(5) <= not release;
|
||||
|
||||
when X"7E" => -- scrolLock RGB/VGA
|
||||
if (VIDEO = '0' and release = '0') then
|
||||
scanSW(6) <= '1';
|
||||
VIDEO <= '1';
|
||||
elsif (VIDEO = '1' and release = '0') then
|
||||
scanSW(6) <= '0';
|
||||
VIDEO <= '0';
|
||||
end if;
|
||||
|
||||
when X"E1" => -- pause
|
||||
if (PAUSE = '0') then
|
||||
scanSW(7) <= '1';
|
||||
PAUSE <= '1';
|
||||
else
|
||||
scanSW(7) <= '0';
|
||||
PAUSE <= '0';
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
nRESET <= '1';
|
||||
|
||||
end architecture;
|
||||
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
-- Copyright (c) 2009-2011 Mike Stirling
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written agreement from the author.
|
||||
--
|
||||
-- * License is granted for non-commercial use only. A fee may not be charged
|
||||
-- for redistributions as source code or in synthesized/hardware form without
|
||||
-- specific prior written agreement from the author.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
-- PS/2 interface (input only)
|
||||
-- Based loosely on ps2_ctrl.vhd (c) ALSE. http://www.alse-fr.com
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- This is input-only for the time being
|
||||
entity ps2_intf is
|
||||
generic (filter_length : positive := 8);
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
nRESET : in std_logic;
|
||||
|
||||
-- PS/2 interface (could be bi-dir)
|
||||
PS2_CLK : in std_logic;
|
||||
PS2_DATA : in std_logic;
|
||||
|
||||
-- Byte-wide data interface - only valid for one clock
|
||||
-- so must be latched externally if required
|
||||
DATA : out std_logic_vector(7 downto 0);
|
||||
VALID : out std_logic
|
||||
-- ;ERROR : out std_logic
|
||||
);
|
||||
end ps2_intf;
|
||||
|
||||
architecture ps2_intf_arch of ps2_intf is
|
||||
subtype filter_t is std_logic_vector(filter_length-1 downto 0);
|
||||
signal clk_filter : filter_t;
|
||||
|
||||
signal ps2_clk_in : std_logic;
|
||||
signal ps2_dat_in : std_logic;
|
||||
-- Goes high when a clock falling edge is detected
|
||||
signal clk_edge : std_logic;
|
||||
signal bit_count : unsigned (3 downto 0);
|
||||
signal shiftreg : std_logic_vector(8 downto 0);
|
||||
signal parity : std_logic;
|
||||
begin
|
||||
-- Register input signals
|
||||
process(nRESET,CLK)
|
||||
begin
|
||||
if nRESET = '0' then
|
||||
ps2_clk_in <= '1';
|
||||
ps2_dat_in <= '1';
|
||||
clk_filter <= (others => '1');
|
||||
clk_edge <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
-- Register inputs (and filter clock)
|
||||
ps2_dat_in <= PS2_DATA;
|
||||
clk_filter <= PS2_CLK & clk_filter(clk_filter'high downto 1);
|
||||
clk_edge <= '0';
|
||||
|
||||
if clk_filter = filter_t'(others => '1') then
|
||||
-- Filtered clock is high
|
||||
ps2_clk_in <= '1';
|
||||
elsif clk_filter = filter_t'(others => '0') then
|
||||
-- Filter clock is low, check for edge
|
||||
if ps2_clk_in = '1' then
|
||||
clk_edge <= '1';
|
||||
end if;
|
||||
ps2_clk_in <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Shift in keyboard data
|
||||
process(nRESET,CLK)
|
||||
begin
|
||||
if nRESET = '0' then
|
||||
bit_count <= (others => '0');
|
||||
shiftreg <= (others => '0');
|
||||
parity <= '0';
|
||||
DATA <= (others => '0');
|
||||
VALID <= '0';
|
||||
-- ERROR <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
-- Clear flags
|
||||
VALID <= '0';
|
||||
-- ERROR <= '0';
|
||||
|
||||
if clk_edge = '1' then
|
||||
-- We have a new bit from the keyboard for processing
|
||||
if bit_count = 0 then
|
||||
-- Idle state, check for start bit (0) only and don't
|
||||
-- start counting bits until we get it
|
||||
|
||||
parity <= '0';
|
||||
|
||||
if ps2_dat_in = '0' then
|
||||
-- This is a start bit
|
||||
bit_count <= bit_count + 1;
|
||||
end if;
|
||||
else
|
||||
-- Running. 8-bit data comes in LSb first followed by
|
||||
-- a single stop bit (1)
|
||||
if bit_count < 10 then
|
||||
-- Shift in data and parity (9 bits)
|
||||
bit_count <= bit_count + 1;
|
||||
shiftreg <= ps2_dat_in & shiftreg(shiftreg'high downto 1);
|
||||
parity <= parity xor ps2_dat_in; -- Calculate parity
|
||||
elsif ps2_dat_in = '1' then
|
||||
-- Valid stop bit received
|
||||
bit_count <= (others => '0'); -- back to idle
|
||||
if parity = '1' then
|
||||
-- Parity correct, submit data to host
|
||||
DATA <= shiftreg(7 downto 0);
|
||||
VALID <= '1';
|
||||
else
|
||||
-- Error
|
||||
-- ERROR <= '1';
|
||||
end if;
|
||||
else
|
||||
-- Invalid stop bit
|
||||
bit_count <= (others => '0'); -- back to idle
|
||||
-- ERROR <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end ps2_intf_arch;
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
module multiboot (
|
||||
input wire clk_icap,
|
||||
input wire REBOOT
|
||||
);
|
||||
|
||||
reg [23:0] spi_addr = 24'h058000; // default: SPI address of second core as defined by the SPI memory map
|
||||
|
||||
reg [4:0] q = 5'b00000;
|
||||
reg reboot_ff = 1'b0;
|
||||
|
||||
always @(posedge clk_icap) begin
|
||||
q[0] <= REBOOT;
|
||||
q[1] <= q[0];
|
||||
q[2] <= q[1];
|
||||
q[3] <= q[2];
|
||||
q[4] <= q[3];
|
||||
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
|
||||
end
|
||||
|
||||
multiboot_spartan6 hacer_multiboot (
|
||||
.CLK(clk_icap),
|
||||
.MBT_RESET(1'b0),
|
||||
.MBT_REBOOT(reboot_ff),
|
||||
.spi_addr(spi_addr)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module multiboot_spartan6 (
|
||||
input wire CLK,
|
||||
input wire MBT_RESET,
|
||||
input wire MBT_REBOOT,
|
||||
input wire [23:0] spi_addr
|
||||
);
|
||||
|
||||
reg [15:0] icap_din;
|
||||
reg icap_ce;
|
||||
reg icap_wr;
|
||||
|
||||
reg [15:0] ff_icap_din_reversed;
|
||||
reg ff_icap_ce;
|
||||
reg ff_icap_wr;
|
||||
|
||||
|
||||
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
|
||||
|
||||
.CE (ff_icap_ce), // Clock enable input
|
||||
.CLK (CLK), // Clock input
|
||||
.I (ff_icap_din_reversed), // 16-bit data input
|
||||
.WRITE (ff_icap_wr) // Write input
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------
|
||||
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
|
||||
// -------------------------------------------------
|
||||
|
||||
|
||||
parameter IDLE = 0,
|
||||
SYNC_H = 1,
|
||||
SYNC_L = 2,
|
||||
|
||||
CWD_H = 3,
|
||||
CWD_L = 4,
|
||||
|
||||
GEN1_H = 5,
|
||||
GEN1_L = 6,
|
||||
|
||||
GEN2_H = 7,
|
||||
GEN2_L = 8,
|
||||
|
||||
GEN3_H = 9,
|
||||
GEN3_L = 10,
|
||||
|
||||
GEN4_H = 11,
|
||||
GEN4_L = 12,
|
||||
|
||||
GEN5_H = 13,
|
||||
GEN5_L = 14,
|
||||
|
||||
NUL_H = 15,
|
||||
NUL_L = 16,
|
||||
|
||||
MOD_H = 17,
|
||||
MOD_L = 18,
|
||||
|
||||
HCO_H = 19,
|
||||
HCO_L = 20,
|
||||
|
||||
RBT_H = 21,
|
||||
RBT_L = 22,
|
||||
|
||||
NOOP_0 = 23,
|
||||
NOOP_1 = 24,
|
||||
NOOP_2 = 25,
|
||||
NOOP_3 = 26;
|
||||
|
||||
|
||||
reg [4:0] state;
|
||||
reg [4:0] next_state;
|
||||
|
||||
|
||||
always @*
|
||||
begin: COMB
|
||||
|
||||
case (state)
|
||||
|
||||
IDLE:
|
||||
begin
|
||||
if (MBT_REBOOT)
|
||||
begin
|
||||
next_state = SYNC_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'hAA99; // Sync word 1
|
||||
end
|
||||
else
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'hFFFF; // Null
|
||||
end
|
||||
end
|
||||
|
||||
SYNC_H:
|
||||
begin
|
||||
next_state = SYNC_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h5566; // Sync word 2
|
||||
end
|
||||
|
||||
SYNC_L:
|
||||
begin
|
||||
next_state = NUL_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
NUL_H:
|
||||
begin
|
||||
// next_state = NUL_L;
|
||||
next_state = GEN1_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
|
||||
end
|
||||
|
||||
//Q
|
||||
|
||||
GEN1_H:
|
||||
begin
|
||||
next_state = GEN1_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
|
||||
end
|
||||
|
||||
GEN1_L:
|
||||
begin
|
||||
next_state = GEN2_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
|
||||
end
|
||||
|
||||
GEN2_H:
|
||||
begin
|
||||
next_state = GEN2_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3281; // Escritura a reg GENERAL_2
|
||||
end
|
||||
|
||||
GEN2_L:
|
||||
begin
|
||||
next_state = MOD_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
|
||||
end
|
||||
|
||||
/////// Registro MODE (para carga a 4x tras reboot)
|
||||
|
||||
MOD_H:
|
||||
begin
|
||||
next_state = MOD_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3301; // Escritura a reg MODE
|
||||
end
|
||||
|
||||
MOD_L:
|
||||
begin
|
||||
next_state = NUL_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
|
||||
end
|
||||
/////
|
||||
|
||||
NUL_L:
|
||||
begin
|
||||
next_state = RBT_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
RBT_H:
|
||||
begin
|
||||
next_state = RBT_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h000E; // REBOOT Command 0x000E
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
RBT_L:
|
||||
begin
|
||||
next_state = NOOP_0;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_0:
|
||||
begin
|
||||
next_state = NOOP_1;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_1:
|
||||
begin
|
||||
next_state = NOOP_2;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_2:
|
||||
begin
|
||||
next_state = NOOP_3;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
NOOP_3:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // NULL value
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // 16'h1111"
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: SEQ
|
||||
if (MBT_RESET)
|
||||
state <= IDLE;
|
||||
else
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: ICAP_FF
|
||||
|
||||
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
|
||||
ff_icap_din_reversed[1] <= icap_din[6];
|
||||
ff_icap_din_reversed[2] <= icap_din[5];
|
||||
ff_icap_din_reversed[3] <= icap_din[4];
|
||||
ff_icap_din_reversed[4] <= icap_din[3];
|
||||
ff_icap_din_reversed[5] <= icap_din[2];
|
||||
ff_icap_din_reversed[6] <= icap_din[1];
|
||||
ff_icap_din_reversed[7] <= icap_din[0];
|
||||
ff_icap_din_reversed[8] <= icap_din[15];
|
||||
ff_icap_din_reversed[9] <= icap_din[14];
|
||||
ff_icap_din_reversed[10] <= icap_din[13];
|
||||
ff_icap_din_reversed[11] <= icap_din[12];
|
||||
ff_icap_din_reversed[12] <= icap_din[11];
|
||||
ff_icap_din_reversed[13] <= icap_din[10];
|
||||
ff_icap_din_reversed[14] <= icap_din[9];
|
||||
ff_icap_din_reversed[15] <= icap_din[8];
|
||||
|
||||
ff_icap_ce <= icap_ce;
|
||||
ff_icap_wr <= icap_wr;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,22 +1,3 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:59:35 01/22/2012
|
||||
-- Design Name:
|
||||
-- Module Name: vdp_timing - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
|
@ -32,9 +13,11 @@ entity rgb_video is
|
|||
color: in std_logic_vector(5 downto 0);
|
||||
hsync: out std_logic;
|
||||
vsync: out std_logic;
|
||||
red: out std_logic_vector(1 downto 0);
|
||||
green: out std_logic_vector(1 downto 0);
|
||||
blue: out std_logic_vector(1 downto 0));
|
||||
red: out std_logic_vector(2 downto 0);
|
||||
green: out std_logic_vector(2 downto 0);
|
||||
blue: out std_logic_vector(2 downto 0)
|
||||
-- ; blank: out std_logic
|
||||
);
|
||||
end rgb_video;
|
||||
|
||||
architecture Behavioral of rgb_video is
|
||||
|
|
@ -121,13 +104,15 @@ vsync <= '1';
|
|||
begin
|
||||
if rising_edge(clk16) then
|
||||
if visible then
|
||||
red <= color(1 downto 0);
|
||||
green <= color(3 downto 2);
|
||||
blue <= color(5 downto 4);
|
||||
red <= color(1 downto 0) & color(1); --Q & color;
|
||||
green <= color(3 downto 2) & color(3); --Q & color;
|
||||
blue <= color(5 downto 4) & color(4); --Q & color;
|
||||
-- blank <= '0';
|
||||
else
|
||||
red <= (others=>'0');
|
||||
green <= (others=>'0');
|
||||
blue <= (others=>'0');
|
||||
-- blank <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,308 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity sms is
|
||||
port (
|
||||
clk: in STD_LOGIC;
|
||||
|
||||
ram_we_n: out STD_LOGIC;
|
||||
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
|
||||
ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
|
||||
|
||||
-- j1_MDsel: out STD_LOGIC; --Q
|
||||
j1_up: in STD_LOGIC;
|
||||
j1_down: in STD_LOGIC;
|
||||
j1_left: in STD_LOGIC;
|
||||
j1_right: in STD_LOGIC;
|
||||
j1_tl: in STD_LOGIC;
|
||||
j1_tr: inout STD_LOGIC;
|
||||
|
||||
audio_l: out STD_LOGIC;
|
||||
audio_r: out STD_LOGIC;
|
||||
|
||||
red: buffer STD_LOGIC_VECTOR(2 downto 0);
|
||||
green: buffer STD_LOGIC_VECTOR(2 downto 0);
|
||||
blue: buffer STD_LOGIC_VECTOR(2 downto 0);
|
||||
hsync: buffer STD_LOGIC;
|
||||
vsync: buffer STD_LOGIC;
|
||||
|
||||
spi_do: in STD_LOGIC;
|
||||
spi_sclk: out STD_LOGIC;
|
||||
spi_di: out STD_LOGIC;
|
||||
spi_cs_n: buffer STD_LOGIC;
|
||||
|
||||
led: out STD_LOGIC;
|
||||
|
||||
ps2_clk: in std_logic;
|
||||
ps2_data: in std_logic;
|
||||
|
||||
NTSC: out std_logic; --Q
|
||||
PAL: out std_logic; --Q
|
||||
|
||||
hdmi_out_p: out std_logic_vector(3 downto 0);
|
||||
hdmi_out_n: out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end sms;
|
||||
|
||||
architecture Behavioral of sms is
|
||||
|
||||
component clock is
|
||||
port (
|
||||
clk_in: in std_logic;
|
||||
sel_pclock: in std_logic;
|
||||
clk_cpu: out std_logic;
|
||||
clk16: out std_logic;
|
||||
clk8: out std_logic;
|
||||
clk32: out std_logic;
|
||||
pclock: out std_logic);
|
||||
end component;
|
||||
|
||||
component system is
|
||||
port (
|
||||
clk_cpu: in STD_LOGIC;
|
||||
clk_vdp: in STD_LOGIC;
|
||||
|
||||
ram_we_n: out STD_LOGIC;
|
||||
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
|
||||
ram_d: inout STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
j1_up: in STD_LOGIC;
|
||||
j1_down: in STD_LOGIC;
|
||||
j1_left: in STD_LOGIC;
|
||||
j1_right: in STD_LOGIC;
|
||||
j1_tl: in STD_LOGIC;
|
||||
j1_tr: inout STD_LOGIC;
|
||||
j2_up: in STD_LOGIC;
|
||||
j2_down: in STD_LOGIC;
|
||||
j2_left: in STD_LOGIC;
|
||||
j2_right: in STD_LOGIC;
|
||||
j2_tl: in STD_LOGIC;
|
||||
j2_tr: inout STD_LOGIC;
|
||||
reset: in STD_LOGIC;
|
||||
-- pause: in STD_LOGIC;
|
||||
|
||||
x: in UNSIGNED(8 downto 0);
|
||||
y: in UNSIGNED(7 downto 0);
|
||||
-- vblank: in STD_LOGIC;
|
||||
-- hblank: in STD_LOGIC;
|
||||
color: out STD_LOGIC_VECTOR(5 downto 0);
|
||||
audio: out STD_LOGIC;
|
||||
|
||||
ps2_clk: in std_logic;
|
||||
ps2_data: in std_logic;
|
||||
|
||||
scanSW: out std_logic;
|
||||
|
||||
spi_do: in STD_LOGIC;
|
||||
spi_sclk: out STD_LOGIC;
|
||||
spi_di: out STD_LOGIC;
|
||||
spi_cs_n: buffer STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
component rgb_video is
|
||||
port (
|
||||
clk16: in std_logic;
|
||||
clk8: in std_logic; --Q
|
||||
x: out unsigned(8 downto 0);
|
||||
y: out unsigned(7 downto 0);
|
||||
vblank: out std_logic;
|
||||
hblank: out std_logic;
|
||||
color: in std_logic_vector(5 downto 0);
|
||||
hsync: out std_logic;
|
||||
vsync: out std_logic;
|
||||
red: out std_logic_vector(2 downto 0);
|
||||
green: out std_logic_vector(2 downto 0);
|
||||
blue: out std_logic_vector(2 downto 0)
|
||||
-- ; blank: out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
COMPONENT MinimalDVID_encoder
|
||||
PORT(
|
||||
clk: IN std_logic;
|
||||
blank: IN std_logic;
|
||||
hsync: IN std_logic;
|
||||
vsync: IN std_logic;
|
||||
red: IN std_logic_vector(2 downto 0);
|
||||
green: IN std_logic_vector(2 downto 0);
|
||||
blue: IN std_logic_vector(2 downto 0);
|
||||
hdmi_p: OUT std_logic_vector(3 downto 0);
|
||||
hdmi_n: OUT std_logic_vector(3 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal clk_cpu: std_logic;
|
||||
signal clk16: std_logic;
|
||||
signal clk8: std_logic;
|
||||
signal clk32: std_logic;
|
||||
|
||||
signal sel_pclock: std_logic;
|
||||
signal blank: std_logic;
|
||||
-- signal blankr: std_logic;
|
||||
|
||||
signal x: unsigned(8 downto 0);
|
||||
signal y: unsigned(7 downto 0);
|
||||
signal vblank: std_logic;
|
||||
signal hblank: std_logic;
|
||||
signal color: std_logic_vector(5 downto 0);
|
||||
signal audio: std_logic;
|
||||
|
||||
signal vga_hsync: std_logic;
|
||||
signal vga_vsync: std_logic;
|
||||
signal vga_red: std_logic_vector(2 downto 0);
|
||||
signal vga_green: std_logic_vector(2 downto 0);
|
||||
signal vga_blue: std_logic_vector(2 downto 0);
|
||||
signal vga_x: unsigned(8 downto 0);
|
||||
signal vga_y: unsigned(7 downto 0);
|
||||
signal vga_vblank: std_logic;
|
||||
signal vga_hblank: std_logic;
|
||||
|
||||
signal rgb_hsync: std_logic;
|
||||
signal rgb_vsync: std_logic;
|
||||
signal rgb_red: std_logic_vector(2 downto 0);
|
||||
signal rgb_green: std_logic_vector(2 downto 0);
|
||||
signal rgb_blue: std_logic_vector(2 downto 0);
|
||||
signal rgb_x: unsigned(8 downto 0);
|
||||
signal rgb_y: unsigned(7 downto 0);
|
||||
signal rgb_vblank: std_logic;
|
||||
signal rgb_hblank: std_logic;
|
||||
|
||||
signal rgb_clk: std_logic;
|
||||
|
||||
-- signal scanDB: std_logic;
|
||||
signal scanSW: std_logic;
|
||||
|
||||
signal j2_tr: std_logic;
|
||||
|
||||
signal c0, c1, c2 : std_logic_vector(9 downto 0); --hdmi
|
||||
|
||||
begin
|
||||
|
||||
clock_inst: clock
|
||||
port map (
|
||||
clk_in => clk,
|
||||
sel_pclock => sel_pclock,
|
||||
clk_cpu => clk_cpu,
|
||||
clk16 => clk16,
|
||||
clk8 => clk8, --clk32 => open
|
||||
clk32 => clk32,
|
||||
pclock => rgb_clk);
|
||||
|
||||
video_inst: rgb_video
|
||||
port map (
|
||||
clk16 => clk16,
|
||||
clk8 => clk8, --Q
|
||||
x => rgb_x,
|
||||
y => rgb_y,
|
||||
vblank => rgb_vblank,
|
||||
hblank => rgb_hblank,
|
||||
color => color,
|
||||
hsync => rgb_hsync,
|
||||
vsync => rgb_vsync,
|
||||
red => rgb_red,
|
||||
green => rgb_green,
|
||||
blue => rgb_blue
|
||||
-- ,blank => blankr
|
||||
);
|
||||
|
||||
video_vga_inst: entity work.vga_video --vga
|
||||
port map (
|
||||
clk16 => clk16,
|
||||
x => vga_x,
|
||||
y => vga_y,
|
||||
vblank => vga_vblank,
|
||||
hblank => vga_hblank,
|
||||
color => color,
|
||||
hsync => vga_hsync,
|
||||
vsync => vga_vsync,
|
||||
red => vga_red,
|
||||
green => vga_green,
|
||||
blue => vga_blue,
|
||||
blank => blank
|
||||
);
|
||||
|
||||
system_inst: system
|
||||
port map (
|
||||
clk_cpu => clk_cpu, --clk_cpu
|
||||
clk_vdp => rgb_clk, --clk8 = rgb --clk16 = vga
|
||||
|
||||
ram_we_n => ram_we_n,
|
||||
ram_a => ram_a,
|
||||
ram_d => ram_d,
|
||||
|
||||
j1_up => j1_up,
|
||||
j1_down => j1_down,
|
||||
j1_left => j1_left,
|
||||
j1_right => j1_right,
|
||||
j1_tl => j1_tl,
|
||||
j1_tr => j1_tr,
|
||||
j2_up => '1',
|
||||
j2_down => '1',
|
||||
j2_left => '1',
|
||||
j2_right => '1',
|
||||
j2_tl => '1',
|
||||
j2_tr => j2_tr,
|
||||
reset => '1',
|
||||
-- pause => '1',
|
||||
|
||||
x => x,
|
||||
y => y,
|
||||
-- vblank => vblank,
|
||||
-- hblank => hblank,
|
||||
color => color,
|
||||
audio => audio,
|
||||
|
||||
ps2_clk => ps2_clk,
|
||||
ps2_data => ps2_data,
|
||||
|
||||
scanSW => scanSW,
|
||||
|
||||
spi_do => spi_do,
|
||||
spi_sclk => spi_sclk,
|
||||
spi_di => spi_di,
|
||||
spi_cs_n => spi_cs_n
|
||||
);
|
||||
|
||||
led <= not spi_cs_n; --Q
|
||||
|
||||
audio_l <= audio;
|
||||
audio_r <= audio;
|
||||
|
||||
NTSC <= '0';
|
||||
PAL <= '1';
|
||||
|
||||
|
||||
vsync <= vga_vsync when scanSW='1' else '1';
|
||||
hsync <= vga_hsync when scanSW='1' else rgb_hsync;
|
||||
red <= vga_red when scanSW='1' else rgb_red;
|
||||
green <= vga_green when scanSW='1' else rgb_green;
|
||||
blue <= vga_blue when scanSW='1' else rgb_blue;
|
||||
|
||||
-- vblank <= vga_vblank when scanSW='1' else rgb_vblank;
|
||||
-- hblank <= vga_hblank when scanSW='1' else rgb_hblank;
|
||||
|
||||
x <= vga_x when scanSW='1' else rgb_x;
|
||||
y <= vga_y when scanSW='1' else rgb_y;
|
||||
|
||||
-- sel_pclock <= '1' when scanDB='1' else '0';
|
||||
sel_pclock <= '1' when scanSW='1' else '0';
|
||||
|
||||
|
||||
--HDMI
|
||||
|
||||
Inst_MinimalDVID_encoder: MinimalDVID_encoder PORT MAP(
|
||||
clk => clk32,
|
||||
blank => blank,
|
||||
hsync => hsync,
|
||||
vsync => vsync,
|
||||
red => red,
|
||||
green => green,
|
||||
blue => blue,
|
||||
hdmi_p => hdmi_out_p,
|
||||
hdmi_n => hdmi_out_n
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity sms_rgb is
|
||||
port (
|
||||
clk: in STD_LOGIC;
|
||||
|
||||
ram_we_n: out STD_LOGIC;
|
||||
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
|
||||
ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
|
||||
|
||||
-- j1_MDsel: out STD_LOGIC; --Q
|
||||
j1_up: in STD_LOGIC;
|
||||
j1_down: in STD_LOGIC;
|
||||
j1_left: in STD_LOGIC;
|
||||
j1_right: in STD_LOGIC;
|
||||
j1_tl: in STD_LOGIC;
|
||||
j1_tr: inout STD_LOGIC;
|
||||
|
||||
audio_l: out STD_LOGIC;
|
||||
audio_r: out STD_LOGIC;
|
||||
|
||||
red: out STD_LOGIC_VECTOR(2 downto 0); --Q
|
||||
green: out STD_LOGIC_VECTOR(2 downto 0); --Q
|
||||
blue: out STD_LOGIC_VECTOR(2 downto 0); --Q
|
||||
hsync: out STD_LOGIC;
|
||||
vsync: out STD_LOGIC;
|
||||
|
||||
spi_do: in STD_LOGIC;
|
||||
spi_sclk: out STD_LOGIC;
|
||||
spi_di: out STD_LOGIC;
|
||||
spi_cs_n: buffer STD_LOGIC; --Q
|
||||
|
||||
led: out STD_LOGIC; --Q
|
||||
|
||||
NTSC : out std_logic; --Q
|
||||
PAL : out std_logic --Q
|
||||
);
|
||||
end sms_rgb;
|
||||
|
||||
architecture Behavioral of sms_rgb is
|
||||
|
||||
component clock is
|
||||
port (
|
||||
clk_in: in std_logic;
|
||||
clk_cpu: out std_logic;
|
||||
clk16: out std_logic;
|
||||
clk32: out std_logic;
|
||||
clk64: out std_logic);
|
||||
end component;
|
||||
|
||||
component system is
|
||||
port (
|
||||
clk_cpu: in STD_LOGIC;
|
||||
clk_vdp: in STD_LOGIC;
|
||||
|
||||
ram_we_n: out STD_LOGIC;
|
||||
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
|
||||
ram_d: inout STD_LOGIC_VECTOR(7 downto 0);
|
||||
|
||||
j1_up: in STD_LOGIC;
|
||||
j1_down: in STD_LOGIC;
|
||||
j1_left: in STD_LOGIC;
|
||||
j1_right: in STD_LOGIC;
|
||||
j1_tl: in STD_LOGIC;
|
||||
j1_tr: inout STD_LOGIC;
|
||||
j2_up: in STD_LOGIC;
|
||||
j2_down: in STD_LOGIC;
|
||||
j2_left: in STD_LOGIC;
|
||||
j2_right: in STD_LOGIC;
|
||||
j2_tl: in STD_LOGIC;
|
||||
j2_tr: inout STD_LOGIC;
|
||||
reset: in STD_LOGIC;
|
||||
pause: in STD_LOGIC;
|
||||
|
||||
x: in UNSIGNED(8 downto 0);
|
||||
y: in UNSIGNED(7 downto 0);
|
||||
vblank: in STD_LOGIC;
|
||||
hblank: in STD_LOGIC;
|
||||
color: out STD_LOGIC_VECTOR(5 downto 0);
|
||||
audio: out STD_LOGIC;
|
||||
|
||||
spi_do: in STD_LOGIC;
|
||||
spi_sclk: out STD_LOGIC;
|
||||
spi_di: out STD_LOGIC;
|
||||
spi_cs_n: out STD_LOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
component rgb_video is
|
||||
port (
|
||||
clk16: in std_logic;
|
||||
clk8: in std_logic; --Q
|
||||
x: out unsigned(8 downto 0);
|
||||
y: out unsigned(7 downto 0);
|
||||
vblank: out std_logic;
|
||||
hblank: out std_logic;
|
||||
color: in std_logic_vector(5 downto 0);
|
||||
hsync: out std_logic;
|
||||
vsync: out std_logic;
|
||||
red: out std_logic_vector(1 downto 0);
|
||||
green: out std_logic_vector(1 downto 0);
|
||||
blue: out std_logic_vector(1 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal clk_cpu: std_logic;
|
||||
signal clk16: std_logic;
|
||||
signal clk8: std_logic;
|
||||
|
||||
signal x: unsigned(8 downto 0);
|
||||
signal y: unsigned(7 downto 0);
|
||||
signal vblank: std_logic;
|
||||
signal hblank: std_logic;
|
||||
signal color: std_logic_vector(5 downto 0);
|
||||
signal audio: std_logic;
|
||||
|
||||
signal j2_tr: std_logic;
|
||||
|
||||
begin
|
||||
|
||||
clock_inst: clock
|
||||
port map (
|
||||
clk_in => clk,
|
||||
clk_cpu => clk_cpu,
|
||||
clk16 => clk16,
|
||||
clk32 => clk8, --clk32 => open
|
||||
clk64 => open);
|
||||
|
||||
video_inst: rgb_video
|
||||
port map (
|
||||
clk16 => clk16,
|
||||
clk8 => clk8, --Q
|
||||
x => x,
|
||||
y => y,
|
||||
vblank => vblank,
|
||||
hblank => hblank,
|
||||
color => color,
|
||||
hsync => hsync,
|
||||
vsync => vsync,
|
||||
red => red(2 downto 1), --Q
|
||||
green => green(2 downto 1), --Q
|
||||
blue => blue(2 downto 1) --Q
|
||||
);
|
||||
|
||||
red(0) <= '0'; --Q
|
||||
green(0) <= '0'; --Q
|
||||
blue(0) <= '0'; --Q
|
||||
|
||||
system_inst: system
|
||||
port map (
|
||||
clk_cpu => clk_cpu, --clk_cpu
|
||||
clk_vdp => clk8, --clk16
|
||||
|
||||
ram_we_n => ram_we_n,
|
||||
ram_a => ram_a,
|
||||
ram_d => ram_d,
|
||||
|
||||
j1_up => j1_up,
|
||||
j1_down => j1_down,
|
||||
j1_left => j1_left,
|
||||
j1_right => j1_right,
|
||||
j1_tl => j1_tl,
|
||||
j1_tr => j1_tr,
|
||||
j2_up => '1',
|
||||
j2_down => '1',
|
||||
j2_left => '1',
|
||||
j2_right => '1',
|
||||
j2_tl => '1',
|
||||
j2_tr => j2_tr,
|
||||
reset => '1',
|
||||
pause => '1',
|
||||
|
||||
x => x,
|
||||
y => y,
|
||||
vblank => vblank,
|
||||
hblank => hblank,
|
||||
color => color,
|
||||
audio => audio,
|
||||
|
||||
spi_do => spi_do,
|
||||
spi_sclk => spi_sclk,
|
||||
spi_di => spi_di,
|
||||
spi_cs_n => spi_cs_n
|
||||
);
|
||||
|
||||
led <= not spi_cs_n; --Q
|
||||
|
||||
audio_l <= audio;
|
||||
audio_r <= audio;
|
||||
|
||||
NTSC <= '0';
|
||||
PAL <= '1';
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
#UCF para el ZX-UNO
|
||||
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
NET "led" LOC="P2" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "red(2)" LOC="P97" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(1)" LOC="P95" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(0)" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(2)" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(1)" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(0)" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET NTSC LOC="P51" | IOSTANDARD = LVCMOS33;
|
||||
NET PAL LOC="P50" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_l" LOC="P98" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_r" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
#NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
#NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
NET ram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(9) LOC="P124 | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET ram_d(0) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(1) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(2) LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(3) LOC="P105" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(4) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(5) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(6) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(7) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
NET ram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "spi_cs_n" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_sclk" LOC="P80" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_di" LOC="P79" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_do" LOC="P81" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
|
||||
# JOYSTICK
|
||||
NET "j1_up" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
#UCF para el ZX-UNO
|
||||
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET NTSC LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
NET PAL LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
#NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
#NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
NET ram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET ram_d(0) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(1) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(2) LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(3) LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(4) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(5) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(6) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(7) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
NET ram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
|
||||
# JOYSTICK
|
||||
NET "j1_up" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tr" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire3" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
#UCF para el ZX-UNO
|
||||
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET NTSC LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
NET PAL LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
#NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
#NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
NET ram_a(0) LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(1) LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(2) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(3) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(4) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(5) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(6) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(7) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(8) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(9) LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(10) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(11) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(12) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(13) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(14) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(15) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(16) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(17) LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(18) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET ram_d(0) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(1) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(2) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(3) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(4) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(5) LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(6) LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(7) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
NET ram_WE_n LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
|
||||
# JOYSTICK
|
||||
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
#UCF para el ZX-UNO
|
||||
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
NET "led" LOC="P11" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "red(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "red(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "blue(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET PAL LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_l" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
#NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
#NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
NET ram_a(0) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(1) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(2) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(3) LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(4) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(5) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(6) LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(7) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(8) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(9) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(10) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(11) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(12) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(13) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(14) LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(15) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(16) LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(17) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_a(18) LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET ram_d(0) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(1) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(2) LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(3) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(4) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(5) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(6) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
NET ram_d(7) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
NET ram_WE_n LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
|
||||
|
||||
# JOYSTICK
|
||||
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
#UCF para el ZX-UNO A+
|
||||
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
|
||||
NET "led" LOC="P2" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "green(0)" LOC="P85" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(0)" LOC="P94" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
|
||||
NET "green(1)" LOC="P87" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(1)" LOC="P95" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
|
||||
NET "green(2)" LOC="P88" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(2)" LOC="P97" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
|
||||
NET "vsync" LOC="P92" | IOSTANDARD=LVCMOS33;
|
||||
NET "hsync" LOC="P93" | IOSTANDARD=LVCMOS33;
|
||||
NET NTSC LOC="P50" | IOSTANDARD=LVCMOS33; #Estos pines van a puerto de expansion
|
||||
NET PAL LOC="P51" | IOSTANDARD=LVCMOS33; #El modelo A+ es amente PAL.
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_l" LOC="P98" | IOSTANDARD=LVCMOS33;
|
||||
NET "audio_r" LOC="P99" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "ps2_clk" LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "ps2_data" LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
NET ram_a(0) LOC="P115" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(1) LOC="P116" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(2) LOC="P117" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(3) LOC="P119" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(4) LOC="P120" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(5) LOC="P123" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(6) LOC="P126" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(7) LOC="P131" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(8) LOC="P127" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(9) LOC="P124" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(10) LOC="P118" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(11) LOC="P121" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(12) LOC="P133" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(13) LOC="P132" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(14) LOC="P137" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(15) LOC="P140" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(16) LOC="P139" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(17) LOC="P141" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(18) LOC="P138" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
|
||||
|
||||
NET ram_d(0) LOC="P114" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(1) LOC="P112" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(2) LOC="P111" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(3) LOC="P105" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(4) LOC="P104" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(5) LOC="P102" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(6) LOC="P101" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(7) LOC="P100" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET ram_WE_n LOC="P134" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
|
||||
NET "spi_do" LOC="P81" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_sclk" LOC="P80" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_di" LOC="P79" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_cs_n" LOC="P78" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "j1_up" LOC="P74" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P67" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P59" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P58" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P66" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_tr" LOC="P75" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
#UCF para el ZX-UNO v2
|
||||
|
||||
NET "CLK" PERIOD=20 ns;
|
||||
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "j1_tr" LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_up" LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
|
||||
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET ram_a(0) LOC="P115" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(1) LOC="P116" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(2) LOC="P117" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(3) LOC="P119" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(4) LOC="P120" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(5) LOC="P123" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(6) LOC="P126" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(7) LOC="P131" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(8) LOC="P127" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(9) LOC="P124" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(10) LOC="P118" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(11) LOC="P121" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(12) LOC="P133" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(13) LOC="P132" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(14) LOC="P137" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(15) LOC="P140" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(16) LOC="P139" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(17) LOC="P141" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(18) LOC="P138" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
|
||||
|
||||
NET ram_d(0) LOC="P114" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(1) LOC="P112" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(2) LOC="P111" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(3) LOC="P99" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(4) LOC="P100" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(5) LOC="P101" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(6) LOC="P102" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(7) LOC="P104" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET ram_WE_n LOC="P134" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET NTSC LOC="P67" | IOSTANDARD=LVCMOS33;
|
||||
NET PAL LOC="P66" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "ps2_data" LOC="P97" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "ps2_clk" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
#UCF para el ZX-UNO v3
|
||||
|
||||
NET "CLK" PERIOD=20 ns;
|
||||
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "j1_tr" LOC="P39" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P7" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_up" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
|
||||
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET ram_a(0) LOC="P143" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(1) LOC="P142" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(2) LOC="P141" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(3) LOC="P140" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(4) LOC="P139" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(5) LOC="P104" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(6) LOC="P102" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(7) LOC="P101" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(8) LOC="P100" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(9) LOC="P99" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(10) LOC="P112" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(11) LOC="P114" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(12) LOC="P115" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(13) LOC="P116" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(14) LOC="P117" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(15) LOC="P131" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(16) LOC="P133" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(17) LOC="P134" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_a(18) LOC="P137" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
|
||||
|
||||
NET ram_d(0) LOC="P132" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(1) LOC="P126" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(2) LOC="P123" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(3) LOC="P120" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(4) LOC="P119" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(5) LOC="P121" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(6) LOC="P124" | IOSTANDARD=LVCMOS33;
|
||||
NET ram_d(7) LOC="P127" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET ram_WE_n LOC="P118" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET NTSC LOC="P67" | IOSTANDARD=LVCMOS33;
|
||||
NET PAL LOC="P66" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "ps2_data" LOC="P97" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "ps2_clk" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
#UCF para el ZX-UNO v4
|
||||
|
||||
NET "CLK" PERIOD=20 ns;
|
||||
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "led" LOC="P11" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "j1_tr" LOC="P8" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_tl" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_right" LOC="P7" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_left" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_down" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "j1_up" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
|
||||
NET "blue(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
|
||||
NET "red(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
|
||||
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "audio_l" LOC="P10" | IOSTANDARD=LVCMOS33;
|
||||
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "ram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "ram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "ram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "ram_d<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "ram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "NTSC" LOC="P66" | IOSTANDARD=LVCMOS33;
|
||||
NET "PAL" LOC="P67" | IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "ps2_data" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
NET "ps2_clk" LOC="P99" | IOSTANDARD=LVCMOS33 | PULLUP;
|
||||
|
||||
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
|
||||
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
|
||||
|
|
@ -11,7 +11,7 @@ entity spi is
|
|||
D_in : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
D_out : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
|
||||
cs_n : out STD_LOGIC;
|
||||
cs_n : buffer STD_LOGIC;
|
||||
sclk : out STD_LOGIC;
|
||||
miso : in STD_LOGIC;
|
||||
mosi : out STD_LOGIC);
|
||||
|
|
|
|||
|
|
@ -26,19 +26,24 @@ entity system is
|
|||
j2_tl: in STD_LOGIC;
|
||||
j2_tr: inout STD_LOGIC;
|
||||
reset: in STD_LOGIC;
|
||||
pause: in STD_LOGIC;
|
||||
-- pause: in STD_LOGIC;
|
||||
|
||||
x: in UNSIGNED(8 downto 0);
|
||||
y: in UNSIGNED(7 downto 0);
|
||||
vblank: in STD_LOGIC;
|
||||
hblank: in STD_LOGIC;
|
||||
-- vblank: in STD_LOGIC;
|
||||
-- hblank: in STD_LOGIC;
|
||||
color: out STD_LOGIC_VECTOR(5 downto 0);
|
||||
audio: out STD_LOGIC;
|
||||
|
||||
ps2_clk: in std_logic;
|
||||
ps2_data: in std_logic;
|
||||
|
||||
scanSW: out std_logic;
|
||||
|
||||
spi_do: in STD_LOGIC;
|
||||
spi_sclk: out STD_LOGIC;
|
||||
spi_di: out STD_LOGIC;
|
||||
spi_cs_n: out STD_LOGIC
|
||||
spi_cs_n: buffer STD_LOGIC
|
||||
);
|
||||
end system;
|
||||
|
||||
|
|
@ -88,8 +93,9 @@ architecture Behavioral of system is
|
|||
D_out: out STD_LOGIC_VECTOR(7 downto 0);
|
||||
x: in unsigned(8 downto 0);
|
||||
y: in unsigned(7 downto 0);
|
||||
vblank: in std_logic;
|
||||
hblank: in std_logic;
|
||||
-- vblank: in std_logic;
|
||||
-- hblank: in std_logic;
|
||||
RST_vram: in std_logic;
|
||||
color: out std_logic_vector (5 downto 0));
|
||||
end component;
|
||||
|
||||
|
|
@ -158,6 +164,20 @@ architecture Behavioral of system is
|
|||
end component;
|
||||
|
||||
signal RESET_n: std_logic;
|
||||
signal resetKey: std_logic;
|
||||
signal MRESET: std_logic;
|
||||
-- signal scanFlag: unsigned := "0";
|
||||
|
||||
-- controles
|
||||
signal p1_up: STD_LOGIC; --0
|
||||
signal p1_down: STD_LOGIC; --1
|
||||
signal p1_left: STD_LOGIC; --2
|
||||
signal p1_right: STD_LOGIC; --3
|
||||
signal p1_tl: STD_LOGIC; --4
|
||||
signal p1_tr: STD_LOGIC; --5
|
||||
signal ctrl_keys: std_logic_vector(7 downto 0);
|
||||
signal Kpause: std_logic := '1';
|
||||
|
||||
signal RD_n: std_logic;
|
||||
signal WR_n: std_logic;
|
||||
signal IRQ_n: std_logic;
|
||||
|
|
@ -195,9 +215,14 @@ architecture Behavioral of system is
|
|||
signal irom_D_out: std_logic_vector(7 downto 0);
|
||||
signal irom_RD_n: std_logic := '1';
|
||||
|
||||
signal bank0: std_logic_vector(4 downto 0); --Q
|
||||
signal bank1: std_logic_vector(4 downto 0); --Q
|
||||
signal bank2: std_logic_vector(4 downto 0); --Q
|
||||
--reset vram
|
||||
signal RST_vram: std_logic;
|
||||
|
||||
signal bank0: std_logic_vector(4 downto 0);
|
||||
signal bank1: std_logic_vector(4 downto 0);
|
||||
signal bank2: std_logic_vector(4 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
|
||||
z80_inst: T80se
|
||||
|
|
@ -208,7 +233,7 @@ begin
|
|||
CLKEN => '1',
|
||||
WAIT_n => '1',
|
||||
INT_n => IRQ_n,
|
||||
NMI_n => pause,
|
||||
NMI_n => Kpause,
|
||||
BUSRQ_n => '1',
|
||||
M1_n => open,
|
||||
MREQ_n => open,
|
||||
|
|
@ -239,8 +264,9 @@ begin
|
|||
D_out => vdp_D_out,
|
||||
x => x,
|
||||
y => y,
|
||||
vblank => vblank,
|
||||
hblank => hblank,
|
||||
-- vblank => vblank,
|
||||
-- hblank => hblank,
|
||||
RST_vram => RST_vram,
|
||||
color => color);
|
||||
|
||||
psg_inst: psg
|
||||
|
|
@ -258,12 +284,12 @@ begin
|
|||
A => A(7 downto 0),
|
||||
D_in => D_in,
|
||||
D_out => io_D_out,
|
||||
J1_up => j1_up,
|
||||
J1_down => j1_down,
|
||||
J1_left => j1_left,
|
||||
J1_right => j1_right,
|
||||
J1_tl => j1_tl,
|
||||
J1_tr => j1_tr,
|
||||
J1_up => p1_up,
|
||||
J1_down => p1_down,
|
||||
J1_left => p1_left,
|
||||
J1_right => p1_right,
|
||||
J1_tl => p1_tl,
|
||||
J1_tr => p1_tr,
|
||||
J2_up => j2_up,
|
||||
J2_down => j2_down,
|
||||
J2_left => j2_left,
|
||||
|
|
@ -301,6 +327,17 @@ begin
|
|||
sclk => spi_sclk,
|
||||
miso => spi_do,
|
||||
mosi => spi_di);
|
||||
|
||||
-- Modulo teclado
|
||||
keyb : entity work.keyboard port map (
|
||||
clk_cpu,
|
||||
ps2_clk,
|
||||
ps2_data,
|
||||
resetKey,
|
||||
MRESET,
|
||||
ctrl_keys
|
||||
);
|
||||
|
||||
|
||||
-- glue logic
|
||||
|
||||
|
|
@ -320,29 +357,38 @@ begin
|
|||
|
||||
spi_WR_n <= bootloader or WR_n when io_n='0' and A(7 downto 5)="110" else '1';
|
||||
|
||||
ram_WR_n <= WR_n when io_n='1' and A(15 downto 14)="11" else '1';
|
||||
ram_WR_n <= WR_n when io_n='1' and A(15 downto 14)="11" else '1';
|
||||
|
||||
rom_WR_n <= bootloader or WR_n when io_n='1' and A(15 downto 14)="10" else '1';
|
||||
|
||||
process (clk_cpu)
|
||||
begin
|
||||
if rising_edge(clk_cpu) then
|
||||
if resetKey = '1' then --q
|
||||
bootloader <= '0';
|
||||
reset_counter <= (others=>'1');
|
||||
--RST_vram <= '1';
|
||||
end if;
|
||||
-- memory control
|
||||
if reset_counter>0 then
|
||||
reset_counter <= reset_counter - 1;
|
||||
elsif ctl_WR_n='0' then
|
||||
elsif ctl_WR_n='0' then --Q
|
||||
if bootloader='0' then
|
||||
bootloader <= '1';
|
||||
reset_counter <= (others=>'1');
|
||||
--RST_vram <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
reset_n <= '0' when reset_counter>0 else '1';
|
||||
|
||||
reset_n <= '0' when reset_counter>0 else '1'; --Q
|
||||
|
||||
irom_D_out <= boot_rom_D_out when bootloader='0' and A(15 downto 14)="00" else rom_D_out;
|
||||
|
||||
process (io_n,A,spi_D_out,vdp_D_out,vdp_D_out,io_D_out,irom_D_out,irom_D_out,irom_D_out,ram_D_out)
|
||||
RST_vram <= '1' when bootloader='0' else '0'; --Q -vram fill
|
||||
|
||||
process (io_n,A,spi_D_out,vdp_D_out,io_D_out,irom_D_out,ram_D_out)
|
||||
begin
|
||||
if io_n='0' then
|
||||
case A(7 downto 5) is
|
||||
|
|
@ -404,5 +450,47 @@ begin
|
|||
ram_d(7 downto 0) <= (others=>'Z') when RD_n='0' else D_in; --Q
|
||||
|
||||
rom_D_out<= ram_d(7 downto 0); --Q
|
||||
|
||||
-----------
|
||||
-- Control tanto por joystick como por teclado
|
||||
-- 0,1,2,3,4,5 = up,dn,l,r,bl,br
|
||||
-- 6 = rgb / vga
|
||||
-- 7 = pause
|
||||
|
||||
p1_up <= ctrl_keys(0) xnor not j1_up;
|
||||
p1_down <= ctrl_keys(1) xnor not j1_down;
|
||||
p1_left <= ctrl_keys(2) xnor not j1_left;
|
||||
p1_right <= ctrl_keys(3) xnor not j1_right;
|
||||
p1_tl <= ctrl_keys(4) xnor not j1_tl;
|
||||
p1_tr <= '0' when ctrl_keys(5)='1' or j1_tr='0' else 'Z';
|
||||
|
||||
|
||||
process (ctrl_keys(7))
|
||||
begin
|
||||
if ctrl_keys(7) = '1' then
|
||||
Kpause <= '0';
|
||||
else
|
||||
Kpause <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (ctrl_keys(6))
|
||||
begin
|
||||
if ctrl_keys(6) = '0' then
|
||||
scanSW <= '0';
|
||||
else
|
||||
scanSW <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
------------multiboot---------------
|
||||
|
||||
multiboot: entity work.multiboot
|
||||
port map(
|
||||
clk_icap => clk_vdp,
|
||||
REBOOT => MRESET
|
||||
);
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
|
|
|||
|
|
@ -14,8 +14,9 @@ entity vdp is
|
|||
D_out: out STD_LOGIC_VECTOR (7 downto 0);
|
||||
x: unsigned(8 downto 0);
|
||||
y: unsigned(7 downto 0);
|
||||
vblank: std_logic;
|
||||
hblank: std_logic;
|
||||
-- vblank: std_logic;
|
||||
-- hblank: std_logic;
|
||||
RST_vram: in std_logic;
|
||||
color: out std_logic_vector (5 downto 0));
|
||||
end vdp;
|
||||
|
||||
|
|
@ -34,7 +35,7 @@ architecture Behavioral of vdp is
|
|||
|
||||
color: out std_logic_vector (5 downto 0);
|
||||
|
||||
display_on: in std_logic;
|
||||
-- display_on: in std_logic;
|
||||
mask_column0: in std_logic;
|
||||
overscan: in std_logic_vector (3 downto 0);
|
||||
|
||||
|
|
@ -45,7 +46,7 @@ architecture Behavioral of vdp is
|
|||
|
||||
spr_address: in std_logic_vector (5 downto 0);
|
||||
spr_high_bit: in std_logic;
|
||||
spr_shift: in std_logic;
|
||||
-- spr_shift: in std_logic;
|
||||
spr_tall: in std_logic);
|
||||
end component;
|
||||
|
||||
|
|
@ -58,7 +59,9 @@ architecture Behavioral of vdp is
|
|||
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
|
||||
vdp_clk: in STD_LOGIC;
|
||||
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
|
||||
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0));
|
||||
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
|
||||
; RST_vram: in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component vdp_cram is
|
||||
|
|
@ -114,6 +117,7 @@ architecture Behavioral of vdp is
|
|||
signal hbl_counter: unsigned(7 downto 0) := (others=>'0');
|
||||
signal vbl_irq: std_logic;
|
||||
signal hbl_irq: std_logic;
|
||||
signal vbi_done: std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
|
|
@ -129,7 +133,7 @@ begin
|
|||
y => y,
|
||||
color => color,
|
||||
|
||||
display_on => display_on,
|
||||
-- display_on => display_on,
|
||||
mask_column0 => mask_column0,
|
||||
overscan => overscan,
|
||||
|
||||
|
|
@ -140,7 +144,7 @@ begin
|
|||
|
||||
spr_address => spr_address,
|
||||
spr_high_bit => spr_high_bit,
|
||||
spr_shift => spr_shift,
|
||||
-- spr_shift => spr_shift,
|
||||
spr_tall => spr_tall);
|
||||
|
||||
vdp_vram_inst: vdp_vram
|
||||
|
|
@ -152,7 +156,9 @@ begin
|
|||
cpu_D_out => vram_cpu_D_out,
|
||||
vdp_clk => vdp_clk,
|
||||
vdp_A => vram_vdp_A,
|
||||
vdp_D_out => vram_vdp_D);
|
||||
vdp_D_out => vram_vdp_D
|
||||
,RST_vram => RST_vram
|
||||
);
|
||||
|
||||
vdp_cram_inst: vdp_cram
|
||||
port map (
|
||||
|
|
@ -218,9 +224,9 @@ begin
|
|||
-- D_out <= (others=>'0');
|
||||
-- when "011" =>
|
||||
-- D_out <= std_logic_vector(y);
|
||||
D_out <= std_logic_vector(y);
|
||||
when "011" =>
|
||||
D_out <= std_logic_vector(x(7 downto 0));
|
||||
D_out <= std_logic_vector(y);
|
||||
when "011" =>
|
||||
D_out <= std_logic_vector(x(7 downto 0));
|
||||
when "100" =>
|
||||
D_out <= vram_cpu_D_out;
|
||||
xram_cpu_A_incr <= '1';
|
||||
|
|
@ -242,17 +248,37 @@ D_out <= std_logic_vector(x(7 downto 0));
|
|||
end process;
|
||||
|
||||
|
||||
process (vdp_clk)
|
||||
-- process (vdp_clk)
|
||||
-- begin
|
||||
-- if rising_edge(vdp_clk) then
|
||||
-- if vblank='1' then
|
||||
-- vbl_irq <= irq_frame_en;
|
||||
-- else
|
||||
-- vbl_irq <= '0';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process (vdp_clk) --q
|
||||
begin
|
||||
if rising_edge(vdp_clk) then
|
||||
if vblank='1' then
|
||||
vbl_irq <= irq_frame_en;
|
||||
if y=0 then
|
||||
vbi_done <= '0';
|
||||
end if;
|
||||
|
||||
if x=256 and y=192 and not (last_y0=std_logic(y(0))) then
|
||||
if(vbi_done='0') then
|
||||
vbl_irq <= irq_frame_en;
|
||||
vbi_done <= '1';
|
||||
end if;
|
||||
else
|
||||
vbl_irq <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--
|
||||
|
||||
process (vdp_clk)
|
||||
begin
|
||||
if rising_edge(vdp_clk) then
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ entity vdp_main is
|
|||
|
||||
color: out std_logic_vector (5 downto 0);
|
||||
|
||||
display_on: in std_logic;
|
||||
-- display_on: in std_logic;
|
||||
mask_column0: in std_logic;
|
||||
overscan: in std_logic_vector (3 downto 0);
|
||||
|
||||
|
|
@ -26,7 +26,7 @@ entity vdp_main is
|
|||
|
||||
spr_address: in std_logic_vector (5 downto 0);
|
||||
spr_high_bit: in std_logic;
|
||||
spr_shift: in std_logic;
|
||||
-- spr_shift: in std_logic;
|
||||
spr_tall: in std_logic);
|
||||
end vdp_main;
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,34 @@ entity vdp_vram is
|
|||
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
|
||||
vdp_clk: in STD_LOGIC;
|
||||
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
|
||||
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0));
|
||||
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
|
||||
;RST_vram: in std_logic
|
||||
);
|
||||
end vdp_vram;
|
||||
|
||||
architecture Behavioral of vdp_vram is
|
||||
|
||||
--Q --vram_fill
|
||||
component vdp_vram_fill is
|
||||
port (
|
||||
cpu_clk: in STD_LOGIC;
|
||||
cpu_WE: in STD_LOGIC;
|
||||
cpu_A: in STD_LOGIC_VECTOR (13 downto 0);
|
||||
cpu_D_in: in STD_LOGIC_VECTOR (7 downto 0);
|
||||
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
|
||||
vdp_clk: in STD_LOGIC;
|
||||
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
|
||||
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal fcpu_D_in: std_logic_vector (7 downto 0);
|
||||
signal scpu_D_out: std_logic_vector (7 downto 0);
|
||||
signal svdp_D_out: std_logic_vector (7 downto 0);
|
||||
signal fcpu_D_out: std_logic_vector (7 downto 0);
|
||||
signal fvdp_D_out: std_logic_vector (7 downto 0);
|
||||
signal fcpu_WE: std_logic;
|
||||
|
||||
begin
|
||||
ram_blocks:
|
||||
for b in 0 to 7 generate
|
||||
|
|
@ -26,7 +50,7 @@ begin
|
|||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(b downto b),
|
||||
DOA => cpu_D_out(b downto b),
|
||||
DOA => scpu_D_out(b downto b),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
|
@ -34,11 +58,29 @@ begin
|
|||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(b downto b),
|
||||
-- DOB => s_D_out(b downto b),
|
||||
DOB => svdp_D_out(b downto b),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
end generate;
|
||||
|
||||
--Q --vram_fill
|
||||
vdp_vram_fill_inst: vdp_vram_fill
|
||||
port map(
|
||||
cpu_clk => cpu_clk,
|
||||
cpu_WE => fcpu_WE,
|
||||
cpu_A => cpu_A,
|
||||
cpu_D_in => cpu_D_in,
|
||||
cpu_D_out => fcpu_D_out,
|
||||
vdp_clk => vdp_clk,
|
||||
vdp_A => vdp_A,
|
||||
vdp_D_out => fvdp_D_out
|
||||
);
|
||||
|
||||
vdp_D_out <= fvdp_D_out when RST_vram='1' else svdp_D_out;
|
||||
cpu_D_out <= fcpu_D_out when RST_vram='1' else scpu_D_out;
|
||||
fcpu_WE <= cpu_WE when RST_vram='1' else '0';
|
||||
|
||||
end Behavioral;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,703 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity vdp_vram_fill is
|
||||
port (
|
||||
cpu_clk : in STD_LOGIC;
|
||||
cpu_WE : in STD_LOGIC;
|
||||
cpu_A : in STD_LOGIC_VECTOR (13 downto 0);
|
||||
cpu_D_in : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
|
||||
vdp_clk : in STD_LOGIC;
|
||||
vdp_A : in STD_LOGIC_VECTOR (13 downto 0);
|
||||
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)
|
||||
);
|
||||
end vdp_vram_fill;
|
||||
|
||||
architecture Behavioral of vdp_vram_fill is
|
||||
begin
|
||||
RAMB16_S1_inst0 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"000000000F000000000000000000000000000000000000000000000000000000",
|
||||
INIT_05 => X"0000000F000000000000000000000000000000000000F0000000000000000000",
|
||||
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000F00000000000000000000000000000F0F00000F",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(0 downto 0),
|
||||
DOA => cpu_D_out(0 downto 0),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(0 downto 0),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst1 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"000000000FF0F00000FF00F0000F00F0000F0F00000000000000000000000000",
|
||||
INIT_05 => X"000000FF000000000000F000000000000000F00000F0F0F00000000000000000",
|
||||
INIT_06 => X"00000FFF00FF000000FFF00F000F000000FF0FF00F000FF00000000000FFFFF0",
|
||||
INIT_07 => X"00000FF00000F000000F0F0000F000F00000000000000000000FFFF000FF0FF0",
|
||||
INIT_08 => X"0FFFF0F00000000F0F00000F000FFF000F00000F00FF0FF00FFFFFF0000FFFF0",
|
||||
INIT_09 => X"00FFFFF00FFFFFFF0FFFFFFF0F0000000F00000F00FFFFFF000000000FFFFFFF",
|
||||
INIT_0A => X"0FFFFFFF0000FFFF00FFFFFF0000000F00FF00F00FF00FF00F00000000000FF0",
|
||||
INIT_0B => X"0000000000000F00000000000FF00000000000000F00000F000000FF0FF000FF",
|
||||
INIT_0C => X"0FFFFF0000000000000FF0000FFFFFFF0000000000FFF0000FFFF00000000000",
|
||||
INIT_0D => X"00FFF0000FFFF0000FFFF000000000000F000F0000000000000000000FFFF000",
|
||||
INIT_0E => X"00FFFF00000FFF000FFFFF000000000000F000000000F000FFFFFF00000FF000",
|
||||
INIT_0F => X"00000000000000F00000000000000000000000000F000F00000FFF000F000F00",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(1 downto 1),
|
||||
DOA => cpu_D_out(1 downto 1),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(1 downto 1),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst2 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"0000000000FFF0F00F0F0FF000FFF0F00FFFFFFF000000FF0000000000000000",
|
||||
INIT_05 => X"00000FF0000000000000F000000000000000F00000FFFFF0000FFF000F00000F",
|
||||
INIT_06 => X"0000FFFF0FFFF00F0FFFFF0F0FFFFFFF0FFFFFFF0F00FFFF000000000FFFFFFF",
|
||||
INIT_07 => X"0000FFFF0000F000000F0F0000F000F0000000000000000000FFFFFF0FFFFFFF",
|
||||
INIT_08 => X"0FFFF0FF0000000F0F00000F00FFFFF00F00000F0FFFFFFF0FFFFFFF0F0F00FF",
|
||||
INIT_09 => X"0FFFFFFF0FFFFFFF0FFFFFFF0F0000000FF000FF0FFFFFFF0F00000F0FFFFFFF",
|
||||
INIT_0A => X"0FFFFFFF00FFFFFF0FFFFFFF0000000F0FFFF0FF0FFFFFFF0FFFFFF00000FFFF",
|
||||
INIT_0B => X"0F00000000000FF00FFFFFFF00FF00000F00000F0F0000FF00000FF000FF0FF0",
|
||||
INIT_0C => X"FFFFFF0000000F0F0F0FFF000FFFFFFF0F000F000FFFFF000FFFFF0000000F00",
|
||||
INIT_0D => X"0FFFFF000FFFFF000FFFFF000F0000000FF0FF000FFFFF0F0F0000000FFFFF00",
|
||||
INIT_0E => X"0FFFFF0000FFFF000FFFFF000F000F000FFF0F000000FF00FFFFFF0000FFFF00",
|
||||
INIT_0F => X"0000000000000FF00000F000000000000F00000F0F00FF0000FFFF000FF0FF00",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(2 downto 2),
|
||||
DOA => cpu_D_out(2 downto 2),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(2 downto 2),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst3 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"000000FF0FFF0FFF0FF0FF000FF0F0FF0FFFFFFF000000FF0F0FFFFF00000000",
|
||||
INIT_05 => X"0000FF000FF000000000F0000FF0000000FFFFF0000FFF0000FFFFF00FF000FF",
|
||||
INIT_06 => X"0FFFF00F0F00F00F0F000F0F0FFFFFFF0F00F00F0F0FF00F0FFFFFFF0F00FF0F",
|
||||
INIT_07 => X"0F0FF00F000F0F00000F0F00000F0F000FF00FF00FF00FF00FF0F00F0F00F00F",
|
||||
INIT_08 => X"0F00F00F0000F00F0F00F00F0FF000FF0F00000F0F00F00F0000F00F0F0FFF0F",
|
||||
INIT_09 => X"0F00000F000FF00000000FF00F00000000FF0FF00F0000000FFFFFFF0000F000",
|
||||
INIT_0A => X"00FF00000FFF00000F0000000FFFFFFF0F0FF00F000FF00F0FFFFFFF0000F00F",
|
||||
INIT_0B => X"0F000000000000FF0FFFFFFF000FF0000F00000F0F000FFF0FFFFF00000FFF00",
|
||||
INIT_0C => X"F0F00F0000000F0F0F0F0F000F000F000F000F000F000F000F0F0F0000000FFF",
|
||||
INIT_0D => X"0F000F0000000F000000FF000FFFFFFF00FFF000FFFFFF0F0FFFFF0F00000F00",
|
||||
INIT_0E => X"0FF000000FF000000F0000000F000F000F0F0F0000000F0000F00F0000F00F00",
|
||||
INIT_0F => X"0000000000000F0000FFFFF00FFFFFFF0FFF0FFF0F0FFF000FF0000000FFF000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(3 downto 3),
|
||||
DOA => cpu_D_out(3 downto 3),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(3 downto 3),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst4 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"00000FFF0F0FF00F000FF0000FF0F0FF000F0F00000000000F0FFFFF00000000",
|
||||
INIT_05 => X"000FF0000FF000000000F000FFF0000000FFFFF0000FFF000FF000FF00FFFFF0",
|
||||
INIT_06 => X"0FFF000F0F00F0FF0F000F0F000F00FF0F00F00F0FFF000F0FFFFFFF0F0FF00F",
|
||||
INIT_07 => X"0F0F000F000F0F00000F0F00000F0F00FFF00FF00FF00FF00F00F00F0F00F00F",
|
||||
INIT_08 => X"0F00000F0000F00F0F00F00F0F00000F0FF000FF0F00F00F0000F00F0F0FFF0F",
|
||||
INIT_09 => X"0F00000F0000FF000000FF000F000000000FFF000F0000000FFFFFFF0000F000",
|
||||
INIT_0A => X"000FF0000FFF00000F0000000FFFFFFF0F00FF0F0000F00F0FF0000F0000F00F",
|
||||
INIT_0B => X"0F000000000000FF0F00000F0000FF000FFFFFFF0F00FF0F0FFFFF00000FFF00",
|
||||
INIT_0C => X"F0F00F000FFFFFFF0F0F0F000F000F000F000F000F000F000F0F0F00000000FF",
|
||||
INIT_0D => X"0F000F0000000F00000FF00000FFFFFF000F0000F000000000FFFF0F00000F00",
|
||||
INIT_0E => X"00FF00000FF000000F0000000FFFFFFF0F0F0F0000000F0000F00F0000F00F00",
|
||||
INIT_0F => X"0000000000000FF00FFF0FFF0FFFFFFF00FFFFF00FFF0F00FFF00000000F0000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(4 downto 4),
|
||||
DOA => cpu_D_out(4 downto 4),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(4 downto 4),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst5 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"00000F000F00FFFF00FF0FF000F0FFF00FFFFFFF000000FF0000000000000000",
|
||||
INIT_05 => X"00FF0000000000000000F000F00000000000F00000FFFFF00F00000F000FFF00",
|
||||
INIT_06 => X"0000000F0FFFFFF00FF00FFF000F0FF00FF000FF0FF000FF00000FF00FFFFFFF",
|
||||
INIT_07 => X"000000FF00F000F0000F0F000000F000F0000000000000000F00FFFF0FFFFFFF",
|
||||
INIT_08 => X"0FFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF00FFFFF00FFFFFFF0FFFFFFF0FF000FF",
|
||||
INIT_09 => X"0FFFFFFF00000FF000000FF00FFFFFFF0000F0000FF000000F00000F0FFFFFFF",
|
||||
INIT_0A => X"00FF000000FFFFFF0FFFFFFF0000000F0FF0FFFF0FFFFFFF0F00000F0FFFFFFF",
|
||||
INIT_0B => X"0F00000000000FF00F00000F00000FF00FFFFFFF0F0FF00F00000FF000FF0FF0",
|
||||
INIT_0C => X"F0FFFF000FFFFFF00FFFFF000FFFFF000FFFFF000FFFFFFF0FFF0F0000000000",
|
||||
INIT_0D => X"0FFFFF000FFFFF000000FF00000000000FFFFFFFF0000000000000000FFFFFFF",
|
||||
INIT_0E => X"0FF0000000FFFF000FFFFF0000FFFFFF0F0FFF000FFFFF0000FFFF00FFFFFF00",
|
||||
INIT_0F => X"00000000000000F00F00000F000000000000F0000FF00F00F0FFFF0000FFF000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(5 downto 5),
|
||||
DOA => cpu_D_out(5 downto 5),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(5 downto 5),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst6 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"000000000FFFFFF00FF0F0F000F00F000FFFFFFF000000FF0000000000000000",
|
||||
INIT_05 => X"0FF00000000000000000F000000000000000F00000F0F0F00000000000000000",
|
||||
INIT_06 => X"0000000F00FFFF0000F00FFF000FFF0000F000F00F0000F000000F0000FFFFF0",
|
||||
INIT_07 => X"000000F000F000F0000F0F000000F000000000000000000000000FF000FF0FF0",
|
||||
INIT_08 => X"00FFFFF00FFFFFFF0FFFFFFF0FFFFFFF000FFF000FFFFFFF0FFFFFF000FFFFF0",
|
||||
INIT_09 => X"00FFFFF00FFFFFFF0FFFFFFF0FFFFFFF0FFFFFFF00F00000000000000FFFFFFF",
|
||||
INIT_0A => X"0FFFFFFF0000FFFF00FFFFFF0000000F00F00FF00FFFFFFF0FFFFFFF0FFFFFFF",
|
||||
INIT_0B => X"0F00000000000F0000000000000000FF000000000FFF000F000000FF0FF000FF",
|
||||
INIT_0C => X"000FF00000000F0000FFF00000FFF00000FFF0000FFFFFFF00F0000000000000",
|
||||
INIT_0D => X"00FFF0000FFFFF000FFFFF00000000000FFFFFFFF0000000000000000FFFFFFF",
|
||||
INIT_0E => X"0FFFFF00000FFF0000FFFF0000000F000F00F0000FFFFF00000FF000FFFFFF00",
|
||||
INIT_0F => X"0000000000000FF00000000000000000000000000F000F00000FFF000FF0FF00",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(6 downto 6),
|
||||
DOA => cpu_D_out(6 downto 6),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(6 downto 6),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
RAMB16_S1_inst7 : RAMB16_S1_S1
|
||||
generic map (
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"0000000000FF00000F00FF0000000000000F0F00000000000000000000000000",
|
||||
INIT_05 => X"0F000000000000000000000000000000000000000000F0000000000000000000",
|
||||
INIT_06 => X"000000000000000000000000000FF00000000000000000000000000000000000",
|
||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_09 => X"000000000FFFFFFF0FFFFFFF000000000FFFFFFF000000000000000000000000",
|
||||
INIT_0A => X"0FFFFFFF000000000000000000000000000000000000000000FFFFF000000000",
|
||||
INIT_0B => X"0F00000000000000000000000000000F000000000FF0000F0000000F0F00000F",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"00000000000000000FFFFF000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"00FFFF0000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0F => X"0000000000000F0000000000000000000000000000000000000000000F000F00",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
||||
)
|
||||
port map (
|
||||
CLKA => cpu_clk,
|
||||
ADDRA => cpu_A,
|
||||
DIA => cpu_D_in(7 downto 7),
|
||||
DOA => cpu_D_out(7 downto 7),
|
||||
ENA => '1',
|
||||
SSRA => '0',
|
||||
WEA => cpu_WE,
|
||||
|
||||
CLKB => not vdp_clk,
|
||||
ADDRB => vdp_A,
|
||||
DIB => "0",
|
||||
DOB => vdp_D_out(7 downto 7),
|
||||
ENB => '1',
|
||||
SSRB => '0',
|
||||
WEB => '0'
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
|
@ -1,22 +1,3 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:59:35 01/22/2012
|
||||
-- Design Name:
|
||||
-- Module Name: vdp_vga_timing - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
|
@ -26,14 +7,16 @@ entity vga_video is
|
|||
clk16: in std_logic;
|
||||
x: out unsigned(8 downto 0);
|
||||
y: out unsigned(7 downto 0);
|
||||
vblank: out std_logic;
|
||||
hblank: out std_logic;
|
||||
vblank: buffer std_logic;
|
||||
hblank: buffer std_logic;
|
||||
color: in std_logic_vector(5 downto 0);
|
||||
hsync: out std_logic;
|
||||
vsync: out std_logic;
|
||||
red: out std_logic_vector(1 downto 0);
|
||||
green: out std_logic_vector(1 downto 0);
|
||||
blue: out std_logic_vector(1 downto 0));
|
||||
red: out std_logic_vector(2 downto 0);
|
||||
green: out std_logic_vector(2 downto 0);
|
||||
blue: out std_logic_vector(2 downto 0)
|
||||
; blank: out std_logic
|
||||
);
|
||||
end vga_video;
|
||||
|
||||
architecture Behavioral of vga_video is
|
||||
|
|
@ -49,9 +32,9 @@ begin
|
|||
process (clk16)
|
||||
begin
|
||||
if rising_edge(clk16) then
|
||||
if hcount=507 then
|
||||
if hcount=511 then --507 = 60Hz , 511 = 50Hz
|
||||
hcount <= (others => '0');
|
||||
if vcount=523 then
|
||||
if vcount=622 then --523 = 60Hz, 623 = 50Hz --622
|
||||
vcount <= (others=>'0');
|
||||
else
|
||||
vcount <= vcount + 1;
|
||||
|
|
@ -62,8 +45,9 @@ begin
|
|||
end if;
|
||||
end process;
|
||||
|
||||
x <= hcount-(91+62);
|
||||
y9 <= vcount(9 downto 1)-(13+27);
|
||||
x <= hcount-(91+60); --62
|
||||
-- y9 <= vcount(9 downto 1)-(13+27); --60Hz
|
||||
y9 <= vcount(9 downto 1)-(13+55);
|
||||
y <= y9(7 downto 0);
|
||||
hblank <= '1' when hcount=0 and vcount(0 downto 0)=0 else '0';
|
||||
vblank <= '1' when hcount=0 and vcount=0 else '0';
|
||||
|
|
@ -71,21 +55,31 @@ begin
|
|||
hsync <= '0' when hcount<61 else '1';
|
||||
vsync <= '0' when vcount<2 else '1';
|
||||
|
||||
visible <= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406;
|
||||
-- visible <= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406; --60Hz
|
||||
visible <= vcount>=35 and vcount<35+580 and hcount>=91 and hcount<91+406; --50Hz
|
||||
|
||||
|
||||
process (clk16)
|
||||
begin
|
||||
if rising_edge(clk16) then
|
||||
if visible then
|
||||
red <= color(1 downto 0);
|
||||
green <= color(3 downto 2);
|
||||
blue <= color(5 downto 4);
|
||||
red <= color(1 downto 0) & color(0); --Q & color
|
||||
green <= color(3 downto 2) & color(2); --Q & color
|
||||
blue <= color(5 downto 4) & color(4); --Q & color
|
||||
-- red <= color(1 downto 0) & '0';
|
||||
-- green <= color(3 downto 2) & '0';
|
||||
-- blue <= color(5 downto 4) & '0';
|
||||
|
||||
blank <= '0';
|
||||
else
|
||||
red <= (others=>'0');
|
||||
red <= (others=>'0');
|
||||
green <= (others=>'0');
|
||||
blue <= (others=>'0');
|
||||
|
||||
blank <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
|
|
|||
Loading…
Reference in New Issue