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antoniovillena
parent
996064bcdc
commit
576bad9c81
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@ -0,0 +1,52 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity disp_shift is
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port(
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clk, reset: in std_logic;
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inp: in std_logic_vector(7 downto 0);
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an: out std_logic_vector(3 downto 0);
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sseg: out std_logic_vector(7 downto 0)
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);
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end disp_shift ;
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architecture arch of disp_shift is
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-- refreshing rate around 800 Hz (50MHz/2^16)
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constant N: integer:=18;
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signal q_reg, q_next: unsigned(N-1 downto 0);
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signal sel: std_logic_vector(1 downto 0);
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begin
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-- register
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process(clk,reset)
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begin
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if reset='1' then
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q_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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q_reg <= q_next;
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end if;
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end process;
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-- next-state logic for the counter
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q_next <= q_reg + 1;
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-- 2 MSBs of counter to control 4-to-1 multiplexing
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-- and to generate active-low enable signal
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sel <= std_logic_vector(q_reg(N-1 downto N-2));
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process(sel,inp)
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begin
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case sel is
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when "00" =>
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an <= "1110";
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sseg <= not ("000" & inp(0) & '0' & inp(1) & "00");
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when "01" =>
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an <= "1101";
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sseg <= not ("000" & inp(2) & '0' & inp(3) & "00");
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when "10" =>
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an <= "1011";
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sseg <= not ("000" & inp(4) & '0' & inp(5) & "00");
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when others =>
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an <= "0111";
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sseg <= not ("000" & inp(6) & '0' & inp(7) & "00");
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end case;
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end process;
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end arch;
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@ -0,0 +1,4 @@
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vhdl work "list_ch03_19_fp.vhd"
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vhdl work "hex_to_sseg.vhd"
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vhdl work "disp_mux.vhd"
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vhdl work "list_ch03_20_fp_test.vhd"
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@ -0,0 +1,30 @@
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-w
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-g Binary:no
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-g Compress
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-g CRC:Enable
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-g Reset_on_err:No
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-g ConfigRate:2
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-g ProgPin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g ExtMasterCclk_en:No
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-g SPI_buswidth:1
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-g TIMER_CFG:0xFFFF
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-g multipin_wakeup:No
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-g StartUpClk:CClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Security:None
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-g DonePipe:No
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-g DriveDone:No
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-g en_sw_gsr:No
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-g drive_awake:No
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-g sw_clk:Startupclk
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-g sw_gwe_cycle:5
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-g sw_gts_cycle:4
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@ -0,0 +1,53 @@
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set -tmpdir "projnav.tmp"
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set -xsthdpdir "xst"
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run
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-ifn fp_adder_test.prj
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-infer_ramb8 No -loop_iteration_limit 32768
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-ofn fp_adder_test
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-ofmt NGC
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-p xc6slx9-2-tqg144
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-top fp_adder_test
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-opt_mode Speed
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-opt_level 2
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-power NO
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-uc "timings.xcf"
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-iuc NO
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-keep_hierarchy No
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-netlist_hierarchy As_Optimized
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints YES
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case Maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-lc Auto
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-reduce_control_sets Auto
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-fsm_extract NO
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-fsm_style LUT
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-shreg_extract YES
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-rom_style Auto
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-auto_bram_packing NO
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-resource_sharing YES
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-async_to_sync YES
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-shreg_min_size 2
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-use_dsp48 Auto
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-iobuf YES
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-max_fanout 100000
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-bufg 16
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-register_duplication YES
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-register_balancing No
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob Auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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@ -11,8 +11,7 @@
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g ExtMasterCclk_en:Yes
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-g ExtMasterCclk_divide:50
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-g ExtMasterCclk_en:No
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-g SPI_buswidth:1
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-g TIMER_CFG:0xFFFF
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-g multipin_wakeup:No
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@ -0,0 +1,39 @@
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-- Listing 3.16
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library ieee;
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use ieee.std_logic_1164.all;
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entity barrel_shifter is
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port(
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a: in std_logic_vector(7 downto 0);
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amt: in std_logic_vector(2 downto 0);
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y: out std_logic_vector(7 downto 0)
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);
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end barrel_shifter ;
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architecture sel_arch of barrel_shifter is
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begin
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with amt select
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y<= a when "000",
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a(0) & a(7 downto 1) when "001",
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a(1 downto 0) & a(7 downto 2) when "010",
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a(2 downto 0) & a(7 downto 3) when "011",
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a(3 downto 0) & a(7 downto 4) when "100",
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a(4 downto 0) & a(7 downto 5) when "101",
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a(5 downto 0) & a(7 downto 6) when "110",
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a(6 downto 0) & a(7) when others; -- 111
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end sel_arch;
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-- Listing 3.17
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architecture multi_stage_arch of barrel_shifter is
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signal s0, s1: std_logic_vector(7 downto 0);
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begin
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-- stage 0, shift 0 or 1 bit
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s0 <= a(0) & a(7 downto 1) when amt(0)='1' else
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a;
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-- stage 1, shift 0 or 2 bits
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s1 <= s0(1 downto 0) & s0(7 downto 2) when amt(1)='1' else
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s0;
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-- stage 2, shift 0 or 4 bits
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y <= s1(3 downto 0) & s1(7 downto 4) when amt(2)='1' else
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s1;
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end multi_stage_arch ;
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@ -0,0 +1,32 @@
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-- Listing 3.18
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity shifter_test is
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port(
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clk: in std_logic;
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bot: in std_logic_vector(4 downto 0);
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sw: in std_logic_vector(7 downto 0);
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led: out std_logic_vector(4 downto 0);
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an: out std_logic_vector(3 downto 0);
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sseg: out std_logic_vector(7 downto 0)
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);
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end shifter_test;
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architecture arch of shifter_test is
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signal miled: std_logic_vector(7 downto 0);
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signal btn : std_logic_vector(2 downto 0);
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begin
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btn <= not (bot(4) & bot (2) & bot(0));
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led <= not bot;
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-- instantiate 7-seg LED display time-multiplexing module
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disp_unit: entity work.disp_shift
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port map(
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clk=>clk, reset=>'0',
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inp=>miled, an=>an, sseg=>sseg);
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shift_unit: entity work.barrel_shifter(multi_stage_arch)
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port map(a=>sw, amt=>btn, y=>miled);
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end arch;
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@ -0,0 +1,106 @@
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-- Listing 3.19
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fp_adder is
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port (
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sign1, sign2: in std_logic;
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exp1, exp2: in std_logic_vector(3 downto 0);
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frac1, frac2: in std_logic_vector(7 downto 0);
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sign_out: out std_logic;
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exp_out: out std_logic_vector(3 downto 0);
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frac_out: out std_logic_vector(7 downto 0)
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);
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end fp_adder ;
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architecture arch of fp_adder is
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-- suffix b, s, a, n for
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-- big, small, aligned, normalized number
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signal signb, signs: std_logic;
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signal expb, exps, expn: unsigned(3 downto 0);
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signal fracb, fracs, fraca, fracn: unsigned(7 downto 0);
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signal sum_norm: unsigned(7 downto 0);
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signal exp_diff: unsigned(3 downto 0);
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signal sum: unsigned(8 downto 0); --one extra for carry
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signal lead0: unsigned(2 downto 0);
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begin
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-- 1st stage: sort to find the larger number
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process (sign1, sign2, exp1, exp2, frac1, frac2)
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begin
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if (exp1 & frac1) > (exp2 & frac2) then
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signb <= sign1;
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signs <= sign2;
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expb <= unsigned(exp1);
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exps <= unsigned(exp2);
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fracb <= unsigned(frac1);
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fracs <= unsigned(frac2);
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else
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signb <= sign2;
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signs <= sign1;
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expb <= unsigned(exp2);
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exps <= unsigned(exp1);
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fracb <= unsigned(frac2);
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fracs <= unsigned(frac1);
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end if;
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end process;
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-- 2nd stage: align smaller number
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exp_diff <= expb - exps;
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with exp_diff select
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fraca <=
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fracs when "0000",
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"0" & fracs(7 downto 1) when "0001",
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"00" & fracs(7 downto 2) when "0010",
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"000" & fracs(7 downto 3) when "0011",
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"0000" & fracs(7 downto 4) when "0100",
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"00000" & fracs(7 downto 5) when "0101",
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"000000" & fracs(7 downto 6) when "0110",
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"0000000" & fracs(7) when "0111",
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"00000000" when others;
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-- 3rd stage: add/substract
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sum <= ('0' & fracb) + ('0' & fraca) when signb=signs else
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('0' & fracb) - ('0' & fraca);
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-- 4th stage: normalize
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-- count leading 0s
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lead0 <= "000" when (sum(7)='1') else
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"001" when (sum(6)='1') else
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"010" when (sum(5)='1') else
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"011" when (sum(4)='1') else
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"100" when (sum(3)='1') else
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"101" when (sum(2)='1') else
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"110" when (sum(1)='1') else
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"111";
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-- shift significand according to leading 0
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with lead0 select
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sum_norm <=
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sum(7 downto 0) when "000",
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sum(6 downto 0) & '0' when "001",
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sum(5 downto 0) & "00" when "010",
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sum(4 downto 0) & "000" when "011",
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sum(3 downto 0) & "0000" when "100",
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sum(2 downto 0) & "00000" when "101",
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sum(1 downto 0) & "000000" when "110",
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sum(0) & "0000000" when others;
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-- normalize with special conditions
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process(sum,sum_norm,expb,lead0)
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begin
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if sum(8)='1' then -- w/ carry out; shift frac to right
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expn <= expb + 1;
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fracn <= sum(8 downto 1);
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elsif (lead0 > expb) then -- too small to normalize;
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expn <= (others=>'0'); -- set to 0
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fracn <= (others=>'0');
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else
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expn <= expb - lead0;
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fracn <= sum_norm;
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end if;
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end process;
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-- form output
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sign_out <= signb;
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exp_out <= std_logic_vector(expn);
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frac_out <= std_logic_vector(fracn);
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end arch;
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|
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@ -0,0 +1,70 @@
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-- Listing 3.20
|
||||
library ieee;
|
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use ieee.std_logic_1164.all;
|
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use ieee.numeric_std.all;
|
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entity fp_adder_test is
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port(
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clk: in std_logic;
|
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bot: in std_logic_vector(4 downto 0);
|
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sw: in std_logic_vector(7 downto 0);
|
||||
led: out std_logic_vector(4 downto 0);
|
||||
an: out std_logic_vector(3 downto 0);
|
||||
sseg: out std_logic_vector(7 downto 0)
|
||||
);
|
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end fp_adder_test;
|
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|
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architecture arch of fp_adder_test is
|
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signal btn: std_logic_vector(3 downto 0);
|
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signal sign1, sign2: std_logic;
|
||||
signal exp1, exp2: std_logic_vector(3 downto 0);
|
||||
signal frac1, frac2: std_logic_vector(7 downto 0);
|
||||
signal sign_out: std_logic;
|
||||
signal exp_out: std_logic_vector(3 downto 0);
|
||||
signal frac_out: std_logic_vector(7 downto 0);
|
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signal led3, led2, led1, led0:
|
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std_logic_vector(6 downto 0);
|
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begin
|
||||
|
||||
btn <= not bot(3 downto 0);
|
||||
led <= not bot;
|
||||
|
||||
-- set up the fp adder input signals
|
||||
sign1 <= '0';
|
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exp1 <= "1000";
|
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frac1<= '1' & sw(1) & sw(0) & "10101";
|
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sign2 <= sw(7);
|
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exp2 <= btn;
|
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frac2 <= '1' & sw(6 downto 0);
|
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|
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-- instantiate fp adder
|
||||
fp_add_unit: entity work.fp_adder
|
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port map(
|
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sign1=>sign1, sign2=>sign2, exp1=>exp1, exp2=>exp2,
|
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frac1=>frac1, frac2=>frac2,
|
||||
sign_out=>sign_out, exp_out=>exp_out,
|
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frac_out=>frac_out
|
||||
);
|
||||
|
||||
-- instantiate three instances of hex decoders
|
||||
-- exponent
|
||||
sseg_unit_0: entity work.hex_to_sseg
|
||||
port map(hex=>exp_out, sseg=>led0);
|
||||
-- 4 LSBs of fraction
|
||||
sseg_unit_1: entity work.hex_to_sseg
|
||||
port map(hex=>frac_out(3 downto 0), sseg=>led1);
|
||||
-- 4 MSBs of fraction
|
||||
sseg_unit_2: entity work.hex_to_sseg
|
||||
port map(hex=>frac_out(7 downto 4), sseg=>led2);
|
||||
-- sign
|
||||
led3 <= "1111110" when sign_out='1' else -- middle bar
|
||||
"1111111"; -- blank
|
||||
|
||||
-- instantiate 7-seg LED display time-multiplexing module
|
||||
disp_unit: entity work.disp_mux
|
||||
port map(
|
||||
clk=>clk, reset=>'0',
|
||||
in0=>led0, in1=>led1, in2=>led2, in3=>led3,
|
||||
point=>'0', colon=>'1',
|
||||
an=>an, sseg=>sseg
|
||||
);
|
||||
end arch;
|
||||
|
|
@ -1,10 +1,15 @@
|
|||
SET machine=hex_to_sseg_test
|
||||
SET speed=2
|
||||
SET ruta_ucf=ch03
|
||||
SET ruta_bat=..\..\
|
||||
rem call %ruta_bat%genxst.bat
|
||||
rem call %ruta_bat%generar.bat v4
|
||||
call :genbitstream hex_to_sseg_test
|
||||
call :genbitstream sm_add_test
|
||||
call :genbitstream shifter_test
|
||||
call :genbitstream fp_adder_test
|
||||
goto :eof
|
||||
|
||||
SET machine=sm_add_test
|
||||
:genbitstream
|
||||
SET machine=%1
|
||||
call %ruta_bat%genxst.bat
|
||||
call %ruta_bat%generar.bat v4
|
||||
call %ruta_bat%generar.bat v4 ZX1
|
||||
copy /y COREn.ZX1 %ruta_bat%.ZX1
|
||||
goto :eof
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
vhdl work "list_ch03_18_shift_test.vhd"
|
||||
vhdl work "list_ch03_16_17_shift.vhd"
|
||||
vhdl work "disp_shift.vhd"
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
-w
|
||||
-g Binary:no
|
||||
-g Compress
|
||||
-g CRC:Enable
|
||||
-g Reset_on_err:No
|
||||
-g ConfigRate:2
|
||||
-g ProgPin:PullUp
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g ExtMasterCclk_en:No
|
||||
-g SPI_buswidth:1
|
||||
-g TIMER_CFG:0xFFFF
|
||||
-g multipin_wakeup:No
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g en_sw_gsr:No
|
||||
-g drive_awake:No
|
||||
-g sw_clk:Startupclk
|
||||
-g sw_gwe_cycle:5
|
||||
-g sw_gts_cycle:4
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
set -tmpdir "projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn shifter_test.prj
|
||||
-infer_ramb8 No -loop_iteration_limit 32768
|
||||
-ofn shifter_test
|
||||
-ofmt NGC
|
||||
-p xc6slx9-2-tqg144
|
||||
-top shifter_test
|
||||
-opt_mode Speed
|
||||
-opt_level 2
|
||||
-power NO
|
||||
-uc "timings.xcf"
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints YES
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case Maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-lc Auto
|
||||
-reduce_control_sets Auto
|
||||
-fsm_extract NO
|
||||
-fsm_style LUT
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-shreg_extract YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-resource_sharing YES
|
||||
-async_to_sync YES
|
||||
-shreg_min_size 2
|
||||
-use_dsp48 Auto
|
||||
-iobuf YES
|
||||
-max_fanout 100000
|
||||
-bufg 16
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob Auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
|
|
@ -11,8 +11,7 @@
|
|||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g ExtMasterCclk_en:Yes
|
||||
-g ExtMasterCclk_divide:50
|
||||
-g ExtMasterCclk_en:No
|
||||
-g SPI_buswidth:1
|
||||
-g TIMER_CFG:0xFFFF
|
||||
-g multipin_wakeup:No
|
||||
|
|
|
|||
Loading…
Reference in New Issue