mirror of https://github.com/zxdos/zxuno.git
Limpio carpeta Jupiter Ace
This commit is contained in:
antoniovillena
parent
803295e691
commit
757d0afa84
|
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@ -1,17 +1,17 @@
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SET machine = "bbc_micro"
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SET machine=bbc_micro
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if not exist projnav.tmp mkdir projnav.tmp
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call xst -intstyle ise -ifn %machine%.xst -ofn %machine%.syr
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call :generar v2 %machine%
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call :generar v3 %machine%
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call :generar v4 %machine%
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call :generar Ap %machine%
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call :generar v2
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call :generar v3
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call :generar v4
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call :generar Ap
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goto :eof
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:generar
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call ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ..\src\%2_zxuno_%1.ucf -p xc6slx9-tqg144-2 %2.ngc %2.ngd
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call map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o %2_map.ncd %2.ngd %2.pcf
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call par -intstyle ise -w -ol high -mt 4 %2_map.ncd %2.ncd %2.pcf
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call trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml %2.twx %2.ncd -o %2.twr %2.pcf
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call bitgen -intstyle ise -f %2.ut %2.ncd
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copy /y %2.bit %2.%1.bit
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call ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ..\src\%machine%_zxuno_%1.ucf -p xc6slx9-tqg144-2 %machine%.ngc %machine%.ngd
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call map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o %machine%_map.ncd %machine%.ngd %machine%.pcf
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call par -intstyle ise -w -ol high -mt 4 %machine%_map.ncd %machine%.ncd %machine%.pcf
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call trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml %machine%.twx %machine%.ncd -o %machine%.twr %machine%.pcf
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call bitgen -intstyle ise -f %machine%.ut %machine%.ncd
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copy /y %machine%.bit %machine%.%1.bit
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:eof
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@ -1,188 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="jupiter_ace.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_jace_spartan6.bgn" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="tld_jace_spartan6.bit" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="tld_jace_spartan6.bld"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="tld_jace_spartan6.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="tld_jace_spartan6.drc" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="tld_jace_spartan6.lso"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6.ncd" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="tld_jace_spartan6.ngc"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="tld_jace_spartan6.ngd"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="tld_jace_spartan6.ngr"/>
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<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="tld_jace_spartan6.pad"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="tld_jace_spartan6.par" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="tld_jace_spartan6.pcf" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tld_jace_spartan6.prj"/>
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<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="tld_jace_spartan6.ptwx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="tld_jace_spartan6.stx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="tld_jace_spartan6.syr"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="tld_jace_spartan6.twr" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="tld_jace_spartan6.twx" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="tld_jace_spartan6.unroutes" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_jace_spartan6.ut" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:fileType="FILE_XPI" xil_pn:name="tld_jace_spartan6.xpi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="tld_jace_spartan6.xst"/>
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<file xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6_guide.ncd" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_jace_spartan6_map.map" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_jace_spartan6_map.mrp" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6_map.ncd" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="tld_jace_spartan6_map.ngm" xil_pn:subbranch="Map"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_map.xrpt"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_ngdbuild.xrpt"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="tld_jace_spartan6_pad.csv" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="tld_jace_spartan6_pad.txt" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_par.xrpt"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_jace_spartan6_summary.html"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="tld_jace_spartan6_summary.xml"/>
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<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="tld_jace_spartan6_usage.xml"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_xst.xrpt"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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||||
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1460482304">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4731562624927410055" xil_pn:start_ts="1460482304">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6263557264038183016" xil_pn:start_ts="1460482304">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1460482304">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1951148348739412805" xil_pn:start_ts="1460482304">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1460482304">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="ReadyToRun"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2932384963007625358" xil_pn:start_ts="1460482304">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="ReadyToRun"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1460482377" xil_pn:in_ck="-1011495219309582457" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5110793382240503873" xil_pn:start_ts="1460482304">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="WarningsGenerated"/>
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||||
<status xil_pn:value="ReadyToRun"/>
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||||
<status xil_pn:value="OutOfDateForOutputs"/>
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||||
<status xil_pn:value="OutputChanged"/>
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||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.lso"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.ngc"/>
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<outfile xil_pn:name="tld_jace_spartan6.ngr"/>
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<outfile xil_pn:name="tld_jace_spartan6.prj"/>
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<outfile xil_pn:name="tld_jace_spartan6.stx"/>
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<outfile xil_pn:name="tld_jace_spartan6.syr"/>
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<outfile xil_pn:name="tld_jace_spartan6.xst"/>
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<outfile xil_pn:name="tld_jace_spartan6_xst.xrpt"/>
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1460482871" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3073422981912245990" xil_pn:start_ts="1460482871">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="ReadyToRun"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1460482887" xil_pn:in_ck="-8973030265980210664" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4306676935314038505" xil_pn:start_ts="1460482871">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.bld"/>
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<outfile xil_pn:name="tld_jace_spartan6.ngd"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6_ngdbuild.xrpt"/>
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||||
</transform>
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<transform xil_pn:end_ts="1460482933" xil_pn:in_ck="-8973030265980210663" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1460482887">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.pcf"/>
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<outfile xil_pn:name="tld_jace_spartan6_map.map"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6_map.mrp"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6_map.ncd"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6_map.ngm"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6_map.xrpt"/>
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<outfile xil_pn:name="tld_jace_spartan6_summary.xml"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6_usage.xml"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1460482979" xil_pn:in_ck="-5559234896413727310" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1460482933">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.ncd"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.pad"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.par"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.ptwx"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.unroutes"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.xpi"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6_pad.csv"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6_pad.txt"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460483026" xil_pn:in_ck="-5273148268032026713" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1664592939731293453" xil_pn:start_ts="1460482979">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.bgn"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.drc"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.ut"/>
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||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460482979" xil_pn:in_ck="-8973030265980210795" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1460482966">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_jace_spartan6.twr"/>
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||||
<outfile xil_pn:name="tld_jace_spartan6.twx"/>
|
||||
</transform>
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||||
</transforms>
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||||
|
||||
</generated_project>
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||||
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|
@ -0,0 +1,13 @@
|
|||
verilog work "tv80_reg.v"
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verilog work "tv80_mcode.v"
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verilog work "tv80_alu.v"
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verilog work "tv80_core.v"
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verilog work "tv80n.v"
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verilog work "rom.v"
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verilog work "ps2_port.v"
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verilog work "memorias.v"
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||||
verilog work "jace_logic.v"
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verilog work "relojes.v"
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verilog work "keyboard_for_ace.v"
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||||
verilog work "fpga_ace.v"
|
||||
verilog work "tld_jace_spartan6.v"
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||||
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|
@ -0,0 +1,30 @@
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|||
-w
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||||
-g Binary:no
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||||
-g Compress
|
||||
-g CRC:Enable
|
||||
-g Reset_on_err:No
|
||||
-g ConfigRate:2
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||||
-g ProgPin:PullUp
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||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g ExtMasterCclk_en:No
|
||||
-g SPI_buswidth:1
|
||||
-g TIMER_CFG:0xFFFF
|
||||
-g multipin_wakeup:No
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g en_sw_gsr:No
|
||||
-g drive_awake:No
|
||||
-g sw_clk:Startupclk
|
||||
-g sw_gwe_cycle:5
|
||||
-g sw_gts_cycle:4
|
||||
|
|
@ -1,427 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="memorias.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="fpga_ace.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_alu.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_reg.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_mcode.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80n.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_core.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="tld_jace_spartan6.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2_port.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="keyboard_for_ace.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="pines_zxuno.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="relojes.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="rom.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="jace_logic.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|tld_jace_spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="tld_jace_spartan6.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/tld_jace_spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="tld_jace_spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="tld_jace_spartan6_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="tld_jace_spartan6_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="tld_jace_spartan6_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="tld_jace_spartan6_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/12.4/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="jupiter_ace_250" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-27T19:18:56" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6E4DA2434A3A4AF5BDCC92DB051566E7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/tld_jace_spartan6" xil_pn:name="pines_zxuno.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
<file xil_pn:name="mapa_teclado_es.vh" xil_pn:type="FILE_VERILOG"/>
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
set -tmpdir "projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn jupiter_ace.prj
|
||||
-ofn jupiter_ace
|
||||
-ofmt NGC
|
||||
-p xc6slx9-2-tqg144
|
||||
-top jupiter_ace
|
||||
-opt_mode Area
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case Maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-lc Auto
|
||||
-reduce_control_sets Auto
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style LUT
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-shreg_extract YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-shreg_min_size 2
|
||||
-use_dsp48 Auto
|
||||
-iobuf YES
|
||||
-max_fanout 100000
|
||||
-bufg 16
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob Auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire2" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire3" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
# Otros
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
|
||||
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
# SRAM
|
||||
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
SET machine=jupiter_ace
|
||||
SET ruta_ucf=jupiter_ace
|
||||
SET ruta_bat=..\
|
||||
call ..\genxst.bat
|
||||
call ..\generar.bat v2_v3
|
||||
call ..\generar.bat v4
|
||||
call ..\generar.bat Ap
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="ParStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>2039</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>10450</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>10450</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>10425</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.4 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>12.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>16.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>17.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>25.6 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>26.4 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>4.1</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>8.6</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.4</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>6.0303</xtag-par-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
</TABLE>
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
#NET "clk12" PERIOD=83 ns;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
#
|
||||
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
#NET "clk12" PERIOD=83 ns;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
#
|
||||
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
#NET "clk12" PERIOD=83 ns;
|
||||
|
||||
# Video output
|
||||
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
// file: tres_relojes.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* CORE_GENERATION_INFO = "tres_relojes,clk_wiz_v1_8,{component_name=tres_relojes,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
|
||||
module cuatro_relojes
|
||||
(// Clock in ports
|
||||
input wire CLK_IN1,
|
||||
// Clock out ports
|
||||
output wire CLK_OUT1,
|
||||
output wire CLK_OUT2,
|
||||
output wire CLK_OUT3,
|
||||
output wire CLK_OUT4
|
||||
);
|
||||
|
||||
wire clkin1,clkout0,clkout1,clkout2,clkout3;
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUFG clkin1_buf
|
||||
(.O (clkin1),
|
||||
.I (CLK_IN1));
|
||||
|
||||
|
||||
// Clocking primitive
|
||||
//------------------------------------
|
||||
// Instantiation of the PLL primitive
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire locked_unused;
|
||||
wire clkfbout;
|
||||
wire clkfbout_buf;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
|
||||
PLL_BASE
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLK_FEEDBACK ("CLKFBOUT"),
|
||||
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (8),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (15),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (60),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_DIVIDE (120),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT3_DIVIDE (30),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKIN_PERIOD (20.0),
|
||||
.REF_JITTER (0.010))
|
||||
pll_base_inst
|
||||
// Output clocks
|
||||
(.CLKFBOUT (clkfbout),
|
||||
.CLKOUT0 (clkout0),
|
||||
.CLKOUT1 (clkout1),
|
||||
.CLKOUT2 (clkout2),
|
||||
.CLKOUT3 (clkout3),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.LOCKED (locked_unused),
|
||||
.RST (1'b0),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf),
|
||||
.CLKIN (clkin1));
|
||||
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf),
|
||||
.I (clkfbout));
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (CLK_OUT1),
|
||||
.I (clkout0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CLK_OUT2),
|
||||
.I (clkout1));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (CLK_OUT3),
|
||||
.I (clkout2));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (CLK_OUT4),
|
||||
.I (clkout3));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
call %ruta_bat%ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc %ruta_ucf%_zxuno_%1.ucf -p xc6slx9-tqg144-2 %machine%.ngc %machine%.ngd
|
||||
call %ruta_bat%map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-2 -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o %machine%_map.ncd %machine%.ngd %machine%.pcf
|
||||
call %ruta_bat%par -intstyle ise -w -ol high -mt 4 %machine%_map.ncd %machine%.ncd %machine%.pcf
|
||||
call %ruta_bat%trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml %machine%.twx %machine%.ncd -o %machine%.twr %machine%.pcf
|
||||
call %ruta_bat%bitgen -intstyle ise -f %machine%.ut %machine%.ncd
|
||||
copy /y %machine%.bit %machine%.%1.bit
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
if not exist projnav.tmp mkdir projnav.tmp
|
||||
call %ruta_bat%xst -intstyle ise -ifn %machine%.xst -ofn %machine%.syr
|
||||
Loading…
Reference in New Issue