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Paso a test21

This commit is contained in:
antoniovillena 2016-05-09 14:07:32 +02:00
parent 33a38487e1
commit 82e75bae28
7 changed files with 773 additions and 736 deletions
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104
cores/Spectrum/audio_management.v
View File

@ -23,64 +23,64 @@
//This is a Delta-Sigma Digital to Analog Converter
module dac (DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
module mixer (
input wire clkdac,
input wire reset,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] ay1,
input wire [7:0] ay2,
output wire audio
);
input wire clkdac,
input wire reset,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] ay1,
input wire [7:0] ay2,
output wire audio
);
reg [9:0] mezcla = 10'h000;
wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 :
({ear,spk,mic}==3'b001)? 8'd36 :
({ear,spk,mic}==3'b010)? 8'd184 :
({ear,spk,mic}==3'b011)? 8'd192 :
({ear,spk,mic}==3'b100)? 8'd22 :
({ear,spk,mic}==3'b101)? 8'd48 :
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
reg [9:0] mezcla = 10'h000;
wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 :
({ear,spk,mic}==3'b001)? 8'd36 :
({ear,spk,mic}==3'b010)? 8'd184 :
({ear,spk,mic}==3'b011)? 8'd192 :
({ear,spk,mic}==3'b100)? 8'd22 :
({ear,spk,mic}==3'b101)? 8'd48 :
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
wire [9:0] mezcla10bits = {2'b00,ay1} + {2'b00,ay2} + {2'b00,beeper} ;
always @(posedge clkdac)
mezcla <= mezcla10bits;
dac audio_dac (
.DACout(audio),
.DACin(mezcla),
.Clk(clkdac),
.Reset(reset)
);
always @(posedge clkdac)
mezcla <= mezcla10bits;
dac audio_dac (
.DACout(audio),
.DACin(mezcla),
.Clk(clkdac),
.Reset(reset)
);
endmodule

10
cores/Spectrum/coreid.v
View File

@ -37,16 +37,16 @@ module coreid (
text[i] = 8'h00;
text[ 0] = "T";
text[ 1] = "2";
text[ 2] = "0";
text[ 2] = "1";
text[ 3] = "-";
text[ 4] = "0";
text[ 5] = "7";
text[ 6] = "1";
text[ 7] = "2";
text[ 5] = "5";
text[ 6] = "0";
text[ 7] = "5";
text[ 8] = "2";
text[ 9] = "0";
text[10] = "1";
text[11] = "5";
text[11] = "6";
end
reg [3:0] textindx = 4'h0;

1122
cores/Spectrum/pll_drp.v
View File

File diff suppressed because it is too large Load Diff

14
cores/Spectrum/ula_radas.v
View File

@ -57,6 +57,7 @@ module ula_radas (
input wire [1:0] mode,
input wire disable_contention,
input wire access_to_contmem,
output wire doc_ext_option,
// Video
output wire [2:0] r,
@ -174,16 +175,17 @@ module ula_radas (
end
// Timex config register
reg [5:0] TimexConfigReg = 6'h00;
reg [7:0] TimexConfigReg = 8'h00;
wire PG = TimexConfigReg[0];
wire HCL = TimexConfigReg[1];
wire HR = TimexConfigReg[2];
assign doc_ext_option = TimexConfigReg[7];
wire [2:0] HRInk = TimexConfigReg[5:3];
always @(posedge clk7) begin
if (rst_n == 1'b0)
TimexConfigReg <= 6'h00;
TimexConfigReg <= 8'h00;
else if (TimexConfigLoad)
TimexConfigReg <= din[5:0];
TimexConfigReg <= din;
end
// Combinational logic between AttrData and AttrOutput
@ -443,7 +445,7 @@ module ula_radas (
// Port 0xFE
always @(posedge clk7) begin
if (iorq_n==1'b0 && wr_n==1'b0) begin
if (a[0]==1'b0) begin
if (a[0]==1'b0 && a[7:0]!=8'hF4) begin
{spk,mic} <= din[4:3];
end
end
@ -457,7 +459,7 @@ module ula_radas (
PaletteLoad = 1'b0;
WriteToPortFE = 1'b0;
if (iorq_n==1'b0 && wr_n==1'b0) begin
if (a[0]==1'b0)
if (a[0]==1'b0 && a[7:0]!=8'hF4)
WriteToPortFE = 1'b1;
else if (a[7:0]==TIMEXPORT)
TimexConfigLoad = 1'b1;
@ -484,7 +486,7 @@ module ula_radas (
always @* begin
dout = 8'hFF;
if (iorq_n==1'b0 && rd_n==1'b0) begin
if (a[0]==1'b0)
if (a[0]==1'b0 && a[7:0]!=8'hF4)
dout = {1'b1,post_processed_ear,1'b1,kbd};
else if (a==ULAPLUSADDR)
dout = {1'b0,PaletteReg};

75
cores/Spectrum/zxuno.v
View File

@ -65,7 +65,7 @@ module zxuno (
input wire joyleft,
input wire joyright,
input wire joyfire,
// MOUSE
inout wire mouseclk,
inout wire mousedata,
@ -140,6 +140,7 @@ module zxuno (
wire issue2_keyboard;
wire disable_contention;
wire access_to_screen;
wire doc_ext_option; // bit 7 del puerto $FF del Timex
// CoreID
wire oe_n_coreid;
@ -218,7 +219,7 @@ module zxuno (
);
ula_radas la_ula (
// Clocks
// Clocks
.clk14(clk14), // 14MHz master clock
.clk7(clk7),
.wssclk(wssclk), // 5MHz WSS clock
@ -226,15 +227,15 @@ module zxuno (
.CPUContention(CPUContention),
.rst_n(mrst_n & rst_n & power_on_reset_n),
// CPU interface
.a(cpuaddr),
// CPU interface
.a(cpuaddr),
.access_to_contmem(access_to_screen),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.int_n(int_n),
.din(cpudout),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.int_n(int_n),
.din(cpudout),
.dout(ula_dout),
.rasterint_enable(rasterint_enable),
.vretraceint_disable(vretraceint_disable),
@ -242,23 +243,24 @@ module zxuno (
.raster_int_in_progress(raster_int_in_progress),
// VRAM interface
.va(vram_addr), // 16KB videoram
.vramdata(vram_dout),
.va(vram_addr), // 16KB videoram, 2 pages
.vramdata(vram_dout),
// I/O ports
.ear(ear),
.mic(mic),
.spk(spk),
.kbd(kbdcol_to_ula),
.issue2_keyboard(issue2_keyboard),
.mode(timing_mode),
.disable_contention(disable_contention),
.ear(ear),
.mic(mic),
.spk(spk),
.kbd(kbdcol_to_ula),
.issue2_keyboard(issue2_keyboard),
.mode(timing_mode),
.disable_contention(disable_contention),
.doc_ext_option(doc_ext_option),
// Video
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.vsync(vsync)
);
@ -303,7 +305,7 @@ module zxuno (
.sd_miso(sd_miso)
);
memory bootrom_rom_y_ram (
new_memory bootrom_rom_y_ram (
// Relojes y reset
.clk(clk), // Reloj del sistema CLK7
.mclk(clk), // Reloj para el modulo de memoria de doble puerto
@ -327,11 +329,16 @@ module zxuno (
// Interface con la ULA
.vramaddr(vram_addr),
.vramdout(vram_dout),
.doc_ext_option(doc_ext_option),
.issue2_keyboard_enabled(issue2_keyboard),
.timing_mode(timing_mode),
.disable_contention(disable_contention),
.access_to_screen(access_to_screen),
// Interface con el bus externo (TO-DO)
.inhibit_rom(1'b0),
.din_external(8'h00),
// Interface para registros ZXUNO
.addr(zxuno_addr),
.ior(zxuno_regrd),
@ -518,21 +525,21 @@ module zxuno (
.oe_n(oe_n_ay),
.audio_out_ay1(ay1_audio),
.audio_out_ay2(ay2_audio)
);
);
///////////////////////////////////
// SOUND MIXER
///////////////////////////////////
// 8-bit mixer to generate different audio levels according to input sources
mixer audio_mix(
.clkdac(clk),
.reset(1'b0),
.mic(mic),
.spk(spk),
mixer audio_mix(
.clkdac(clk),
.reset(1'b0),
.mic(mic),
.spk(spk),
.ear(ear),
.ay1(ay1_audio),
.ay2(ay2_audio),
.audio(audio_out)
);
.ay2(ay2_audio),
.audio(audio_out)
);
endmodule

138
firmware/firmware.asm
View File

@ -22,6 +22,7 @@
define scandbl_ctrl 11
define raster_line 12
define raster_ctrl 13
define dev_control 14
define core_addr $fc
define core_boot $fd
define cold_boot $fe
@ -910,7 +911,37 @@ romsb sub $1e-$16
jp z, roms27
sub $6e-$1f ; n= New Entry
jp nz, roms144
call loadta
call qloadt
ld ix, cad54
call_prnstr
dec c
ld a, %01000111 ; fondo blanco tinta azul
ld h, $12
ld l, c
ld de, $0201
call window
ld c, l
ld hl, $0200
ld b, $18
call inputv
; push bc
; push hl
ld a, (codcnt)
rrca
ret nc
call atoi
call isbusy
ld bc, $090a
; pop hl
; pop bc
jr nc, romsb5
ld ix, cad113
call_prnstr
call_prnstr
call_prnstr
jp waitky
romsb5 call loadta
jp nc, roms12
ld hl, %00001010
romsc ld (offsel), hl
@ -937,21 +968,8 @@ romsd dec iyh
jr nz, romsc
ei
call romcyb
ld ix, cad54
call_prnstr
dec c
ld a, %01000111 ; fondo blanco tinta azul
ld h, $12
ld l, c
ld de, $0201
call window
ld c, l
ld hl, $0200
ld b, $18
call inputv
ld a, (codcnt)
rrca
ret nc
call newent
call atoi
ld (items), a
@ -1237,6 +1255,18 @@ roms27 ld hl, $0104
ld a, (codcnt)
jp main13
isbusy ld hl, indexe
ld b, a
isbus1 ld a, (hl) ; calculo en L el número de entradas
inc l
inc a
jr nz, isbus1
ld a, l
ret
ret
;*** Upgrade Menu ***
;*********************
upgra ld bc, (menuop)
@ -1627,8 +1657,10 @@ buub ld a, (de)
inc de
jr nz, beeb
djnz buub
beeb jr z, bien
pop hl
pop ix
sali pop bc
jr desc
beeb pop hl
pop bc
ld de, $0020
add hl, de
@ -1639,9 +1671,6 @@ desc pop hl
pop de
pop bc
ret
bien pop ix
sali pop bc
jr desc
trans push bc
ld a, (tmpbu2+$d)
@ -2145,6 +2174,23 @@ addbl1 inc iyl
sub iyl
ret
;first part of loadta
qloadt ld ix, cad49
call prnhel
call bloq1
dec c
dec c
ld iyl, 5
loadt1 ld ix, cad42
call_prnstr
dec iyl
jr nz, loadt1
ld ixl, cad43 & $ff
call_prnstr
ld ixl, cad44 & $ff
ld c, b
call_prnstr
; -------------------------------------
; Prits a blank line in the actual line
; -------------------------------------
@ -2199,22 +2245,7 @@ shaon ld a, $0f
; -------------------------------------
; Shows the window of Load from Tape
; -------------------------------------
loadta ld ix, cad49
call prnhel
call bloq1
dec c
dec c
ld iyl, 5
loadt1 ld ix, cad42
call_prnstr
dec iyl
jr nz, loadt1
ld ixl, cad43 & $ff
call_prnstr
ld ixl, cad44 & $ff
ld c, b
call_prnstr
call romcyb
loadta call qloadt
ld ix, cad45
call_prnstr
ld ix, tmpbuf
@ -3204,7 +3235,7 @@ conti di
call calcu
push hl
pop ix
ld d, (ix+6)
ld d, (ix+2)
ld hl, timing
ld a, 3
cp (hl) ; timing
@ -3269,22 +3300,16 @@ conti3 ld de, $c000 | master_mapper
inc a
cp 24
jr nz, conti3
defb $c2
conti35 dec iyl
jr nz, conti5
conti4 ld a, (ix+1)
ld iyl, a
ld a, (ix)
ld iyh, a
conti5 ld a, iyh
inc iyh
conti4 ld iyl, 8
conti5 ld a, (ix)
inc (ix)
call alto slot2a
ld a, master_mapper
dec b
out (c), a
inc b
ld a, (ix+2)
inc (ix+2)
ld a, iyl
inc iyl
out (c), a
ld de, $c000
ld a, $40
@ -3321,18 +3346,18 @@ conti6 in a, (c)
jr z, conti6
conti7 pop bc
pop ix
conti8 dec (ix+3)
jr nz, conti35
conti8 dec (ix+1)
jr nz, conti5
conti9 ld a, 0
dec b
out (c), 0;d
inc b
out (c), a
ld bc, $1ffd
ld a, (ix+4)
dec b
ld a, dev_control
out (c), a
ld b, $7f
ld a, (ix+5)
inc b
ld a, (ix+3)
out (c), a
rst 0
@ -4455,6 +4480,9 @@ cad109 defb '63.8', 0
cad110 defb '1X', 0
cad111 defb '2X', 0
cad112 defb 'Break to exit', 0
cad113 defb 'Slot occupied, select', 0
defb 'another or delete a', 0
defb 'ROM to free it', 0
;cad199 defb 'af0000 bc0000 de0000 hl0000 sp0000 ix0000 iy0000', 0
fincad

46
firmware/generamcs.bat
View File

@ -19,27 +19,27 @@ call :CreateMachine CORE8 "Acorn Atom (VGA)" AcornAtom\AcornAtom.%2.bit 0 %3
call :CreateMachine CORE9 "NES (VGA)" NES\xilinx\nes_zxuno.%2.bit 0 %3
copy /y rom_binaries\esxdos.rom sd_binaries\ESXDOS.%3
copy /y firmware.rom sd_binaries\FIRMWARE.%3
GenRom 0 202 0 0 0 BIOS firmware.rom core_taps\FIRMWARE.TAP
GenRom 0 0 0 0 0 ESXDOS rom_binaries\esxdos.rom core_taps\ESXDOS.TAP
call :CreateRom 0 "ZX Spectrum 48K Cargando Leches" leches dn 8 4 0 0
call :CreateRom 1 "ZX +3e DivMMC" plus3en40divmmc t 8 4 0 0
call :CreateRom 5 "SE Basic IV 4.0 Anya" se d 8 4 0 0
call :CreateRom 7 "ZX Spectrum 48K" 48 dn 8 4 0 32
call :CreateRom 8 "Jet Pac (1983)" JetPac 0 8 1 0 32
call :CreateRom 9 "Pssst (1983)" Pssst 0 8 1 0 32
call :CreateRom 10 "Cookie (1983)" Cookie 0 8 1 0 32
call :CreateRom 11 "Tranz Am (1983)" TranzAm 0 8 1 0 32
call :CreateRom 12 "Master Chess (1983)" MasterChess 0 8 1 0 32
call :CreateRom 13 "Backgammon (1983)" Backgammon 0 8 1 0 32
call :CreateRom 14 "Hungry Horace (1983)" HungryHorace 0 8 1 0 32
call :CreateRom 15 "Horace & the Spiders (1983)" HoraceSpiders 0 8 1 0 32
call :CreateRom 16 "Planetoids (1983)" Planetoids 0 8 1 0 32
call :CreateRom 17 "Space Raiders (1983)" SpaceRaiders 0 8 1 0 32
call :CreateRom 18 "Deathchase (1983)" Deathchase 0 8 1 0 32
call :CreateRom 19 "Manic Miner (1983)" ManicMiner 0 8 1 0 32
call :CreateRom 20 "Misco Jones (2013)" MiscoJones 0 8 1 0 32
call :CreateRom 21 "Jet Set Willy (1984)" JetSetWilly 0 8 1 0 32
call :CreateRom 22 "Lala Prologue (2010)" LalaPrologue 0 8 1 0 32
GenRom 0 sf1t BIOS firmware.rom core_taps\FIRMWARE.TAP
GenRom 0 0 ESXDOS rom_binaries\esxdos.rom core_taps\ESXDOS.TAP
call :CreateRom 0 "ZX Spectrum 48K Cargando Leches" leches dn 0
call :CreateRom 1 "ZX +3e DivMMC" plus3en40divmmc t 0
call :CreateRom 5 "SE Basic IV 4.0 Anya" se d 0
call :CreateRom 7 "ZX Spectrum 48K" 48 dn 17
call :CreateRom 8 "Jet Pac (1983)" JetPac 0 17
call :CreateRom 9 "Pssst (1983)" Pssst 0 17
call :CreateRom 10 "Cookie (1983)" Cookie 0 17
call :CreateRom 11 "Tranz Am (1983)" TranzAm 0 17
call :CreateRom 12 "Master Chess (1983)" MasterChess 0 17
call :CreateRom 13 "Backgammon (1983)" Backgammon 0 17
call :CreateRom 14 "Hungry Horace (1983)" HungryHorace 0 17
call :CreateRom 15 "Horace & the Spiders (1983)" HoraceSpiders 0 17
call :CreateRom 16 "Planetoids (1983)" Planetoids 0 17
call :CreateRom 17 "Space Raiders (1983)" SpaceRaiders 0 17
call :CreateRom 18 "Deathchase (1983)" Deathchase 0 17
call :CreateRom 19 "Manic Miner (1983)" ManicMiner 0 17
call :CreateRom 20 "Misco Jones (2013)" MiscoJones 0 17
call :CreateRom 21 "Jet Set Willy (1984)" JetSetWilly 0 17
call :CreateRom 22 "Lala Prologue (2010)" LalaPrologue 0 17
srec_cat FLASH.ZX1 -binary ^
-o prom.%2.mcs -Intel ^
-line-length=44 ^
@ -54,13 +54,13 @@ IF EXIST ..\cores\%3 (
) ELSE (
Bit2Bin ..\cores\%4 sd_binaries\%1.%5
)
GenRom 0 0 0 0 0 %2 sd_binaries\%1.%5 core_taps\%1.TAP
GenRom 0 0 %2 sd_binaries\%1.%5 core_taps\%1.TAP
AddItem %1 core_taps\%1.tap
rem CgLeches core_taps\%1.TAP core_wavs\%1.WAV 4
goto :eof
:CreateRom
GenRom %4 %5 %6 %7 %8 %2 rom_binaries\%3.rom rom_taps\%3.tap
GenRom %4 %5 %2 rom_binaries\%3.rom rom_taps\%3.tap
AddItem ROM %1 rom_taps\%3.tap
rem CgLeches rom_taps\%3.tap rom_wavs\%3.wav 4
:eof