Actualizo Master System

This commit is contained in:
antoniovillena 2016-05-04 20:12:08 +02:00
parent 8365ef5bc9
commit c5e731222b
11 changed files with 471 additions and 688 deletions

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@ -1,495 +0,0 @@
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<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="sms_rgb" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="sms_rgb_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="sms_rgb_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="sms_rgb_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="sms_rgb_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="sms_rgb" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="src/sms_zxuno.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="P:/Xilinx/12.4/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|main_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-08-24T17:49:03" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C96AC770BEAC44FA8345C5AE67591974" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/sms_rgb" xil_pn:name="src/sms.bmm"/>
<binding xil_pn:location="/sms_vga" xil_pn:name="src/sms.bmm"/>
<binding xil_pn:location="/sms_rgb" xil_pn:name="src/sms_zxuno.ucf"/>
<binding xil_pn:location="/sms_vga" xil_pn:name="src/sms_zxuno.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

View File

@ -0,0 +1,25 @@
vhdl work "src/vdp_sprite_shifter.vhd"
vhdl work "T80/T80_Reg.vhd"
vhdl work "T80/T80_Pack.vhd"
vhdl work "T80/T80_MCode.vhd"
vhdl work "T80/T80_ALU.vhd"
vhdl work "src/vdp_sprites.vhd"
vhdl work "src/vdp_background.vhd"
vhdl work "T80/T80.vhd"
vhdl work "src/vdp_vram.vhd"
vhdl work "src/vdp_main.vhd"
vhdl work "src/vdp_cram.vhd"
vhdl work "src/psg_tone.vhd"
vhdl work "src/psg_noise.vhd"
vhdl work "src/dac.vhd"
vhdl work "T80/T80se.vhd"
vhdl work "src/vdp.vhd"
vhdl work "src/spi.vhd"
vhdl work "src/ram.vhd"
vhdl work "src/psg.vhd"
vhdl work "src/io.vhd"
vhdl work "src/bootloader_rom.vhd"
vhdl work "src/system.vhd"
vhdl work "src/rgb_video.vhd"
vhdl work "src/clocks.vhd"
vhdl work "src/sms_rgb.vhd"

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-w
-g Binary:no
-g Compress
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:4
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

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set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn sms_rgb.prj
-ofn sms_rgb
-ofmt NGC
-p xc6slx9-3-tqg144
-top sms_rgb
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

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@ -1,55 +0,0 @@
// BMM LOC annotation file.
//
// Release 14.6 - P.20131013, build 3.0.10 Apr 3, 2013
// Copyright (c) 1995-2015 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'bootrom', ID 0, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP bootrom PPC405 0
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'bootrom' address space 'boot_code' 0x00000000:0x00003FFF (16 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE boot_code RAMB16 [0x00000000:0x00003FFF]
BUS_BLOCK
system_inst/boot_rom_inst/ram_blocks[7].inst RAMB16 [7:7] [0:16383] PLACED = X1Y4;
system_inst/boot_rom_inst/ram_blocks[6].inst RAMB16 [6:6] [0:16383] PLACED = X1Y6;
system_inst/boot_rom_inst/ram_blocks[5].inst RAMB16 [5:5] [0:16383] PLACED = X1Y10;
system_inst/boot_rom_inst/ram_blocks[4].inst RAMB16 [4:4] [0:16383] PLACED = X1Y8;
system_inst/boot_rom_inst/ram_blocks[3].inst RAMB16 [3:3] [0:16383] PLACED = X1Y12;
system_inst/boot_rom_inst/ram_blocks[2].inst RAMB16 [2:2] [0:16383] PLACED = X1Y24;
system_inst/boot_rom_inst/ram_blocks[1].inst RAMB16 [1:1] [0:16383] PLACED = X1Y22;
system_inst/boot_rom_inst/ram_blocks[0].inst RAMB16 [0:0] [0:16383] PLACED = X1Y26;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'bootrom' address space 'vram_code' 0x00008000:0x0000BFFF (16 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE vram_code RAMB16 [0x00008000:0x0000BFFF]
BUS_BLOCK
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[7].inst RAMB16 [7:7] [0:16383] PLACED = X0Y10;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[6].inst RAMB16 [6:6] [0:16383] PLACED = X0Y12;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[5].inst RAMB16 [5:5] [0:16383] PLACED = X0Y14;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[4].inst RAMB16 [4:4] [0:16383] PLACED = X0Y24;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[3].inst RAMB16 [3:3] [0:16383] PLACED = X0Y22;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[2].inst RAMB16 [2:2] [0:16383] PLACED = X0Y20;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[1].inst RAMB16 [1:1] [0:16383] PLACED = X0Y18;
system_inst/vdp_inst/vdp_vram_inst/ram_blocks[0].inst RAMB16 [0:0] [0:16383] PLACED = X0Y16;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

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#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "led" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
NET "red(2)" LOC="P97" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P95" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P94" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P51" | IOSTANDARD = LVCMOS33;
NET PAL LOC="P50" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P98" | IOSTANDARD = LVCMOS33;
NET "audio_r" LOC="P99" | IOSTANDARD = LVCMOS33;
#NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
#NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET ram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(9) LOC="P124 | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET ram_d(0) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(1) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(2) LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(3) LOC="P105" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(4) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(5) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(6) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(7) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "spi_cs_n" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_sclk" LOC="P80" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_di" LOC="P79" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_do" LOC="P81" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
# JOYSTICK
NET "j1_up" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;

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#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P67" | IOSTANDARD = LVCMOS33;
NET PAL LOC="P66" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
#NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
#NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET ram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET ram_d(0) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(1) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(2) LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(3) LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(4) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(5) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(6) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(7) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;
# JOYSTICK
NET "j1_up" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;

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#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P67" | IOSTANDARD = LVCMOS33;
NET PAL LOC="P66" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
#NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
#NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET ram_a(0) LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(1) LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(2) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(3) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(4) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(5) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(6) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(7) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(8) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(9) LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(10) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(11) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(12) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(13) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(14) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(15) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(16) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(17) LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(18) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET ram_d(0) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(1) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(2) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(3) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(4) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(5) LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(6) LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(7) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_WE_n LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
# JOYSTICK
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;

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#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "led" LOC="P11" | IOSTANDARD = LVCMOS33;
# Video output
NET "red(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
NET PAL LOC="P67" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
#NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
#NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET ram_a(0) LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(1) LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(2) LOC="P137" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(3) LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(4) LOC="P133" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(5) LOC="P120" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(6) LOC="P118" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(7) LOC="P116" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(8) LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(9) LOC="P112" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(10) LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(11) LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(12) LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(13) LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(14) LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(15) LOC="P131" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(16) LOC="P138" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(17) LOC="P140" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_a(18) LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET ram_d(0) LOC="P132" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(1) LOC="P127" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(2) LOC="P124" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(3) LOC="P123" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(4) LOC="P115" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(5) LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(6) LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_d(7) LOC="P126" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
NET ram_WE_n LOC="P121" | IOSTANDARD = LVCMOS33 | SLEW=FAST;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST;
# JOYSTICK
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;

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@ -1,69 +0,0 @@
#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD=LVCMOS33 ; # CLK
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
NET "j1_tr" LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_right" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_left" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_down" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_up" LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B1
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B2
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B3
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B4
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
NET ram_a(0) LOC="P115" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR0
NET ram_a(1) LOC="P116" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR1
NET ram_a(2) LOC="P117" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR2
NET ram_a(3) LOC="P119" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR3
NET ram_a(4) LOC="P120" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR4
NET ram_a(5) LOC="P123" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR5
NET ram_a(6) LOC="P126" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR6
NET ram_a(7) LOC="P131" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR7
NET ram_a(8) LOC="P127" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR8
NET ram_a(9) LOC="P124" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR9
NET ram_a(10) LOC="P118" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR10
NET ram_a(11) LOC="P121" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR11
NET ram_a(12) LOC="P133" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR12
NET ram_a(13) LOC="P132" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR13
NET ram_a(14) LOC="P137" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR14
NET ram_a(15) LOC="P140" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR15
NET ram_a(16) LOC="P139" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR16
NET ram_a(17) LOC="P141" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR17
NET ram_a(18) LOC="P138" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR18
NET ram_d(0) LOC="P114" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA0
NET ram_d(1) LOC="P112" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA1
NET ram_d(2) LOC="P111" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA2
NET ram_d(3) LOC="P99" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA3
NET ram_d(4) LOC="P100" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA4
NET ram_d(5) LOC="P101" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA5
NET ram_d(6) LOC="P102" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA6
NET ram_d(7) LOC="P104" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA7
NET ram_WE_n LOC="P134" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # nWE
NET NTSC LOC = "P67" | IOSTANDARD = LVCMOS33;
NET PAL LOC = "P66" | IOSTANDARD = LVCMOS33;

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@ -1,69 +0,0 @@
#UCF para el ZX-UNO
NET CLK LOC="P55" | IOSTANDARD=LVCMOS33 ; # CLK
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
NET "j1_tr" LOC="P39" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_up" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B1
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B2
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B3
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33 | DRIVE=8 | SLEW=FAST; # B4
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
NET ram_a(0) LOC="P143" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR0
NET ram_a(1) LOC="P142" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR1
NET ram_a(2) LOC="P141" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR2
NET ram_a(3) LOC="P140" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR3
NET ram_a(4) LOC="P139" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR4
NET ram_a(5) LOC="P104" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR5
NET ram_a(6) LOC="P102" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR6
NET ram_a(7) LOC="P101" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR7
NET ram_a(8) LOC="P100" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR8
NET ram_a(9) LOC="P99" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR9
NET ram_a(10) LOC="P112" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR10
NET ram_a(11) LOC="P114" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR11
NET ram_a(12) LOC="P115" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR12
NET ram_a(13) LOC="P116" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR13
NET ram_a(14) LOC="P117" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR14
NET ram_a(15) LOC="P131" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR15
NET ram_a(16) LOC="P133" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR16
NET ram_a(17) LOC="P134" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR17
NET ram_a(18) LOC="P137" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # ADDR18
NET ram_d(0) LOC="P132" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA0
NET ram_d(1) LOC="P126" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA1
NET ram_d(2) LOC="P123" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA2
NET ram_d(3) LOC="P120" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA3
NET ram_d(4) LOC="P119" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA4
NET ram_d(5) LOC="P121" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA5
NET ram_d(6) LOC="P124" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA6
NET ram_d(7) LOC="P127" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # DATA7
NET ram_WE_n LOC="P118" | IOSTANDARD=LVCMOS33 | SLEW=FAST; # nWE
NET NTSC LOC = "P67" | IOSTANDARD = LVCMOS33;
NET PAL LOC = "P66" | IOSTANDARD = LVCMOS33;