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This commit is contained in:
antoniovillena 2016-05-04 19:02:06 +02:00
parent 757d0afa84
commit 8365ef5bc9
3 changed files with 4 additions and 4 deletions
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2
cores/JupiterAce/fpga_ace.v
View File

@ -21,7 +21,7 @@
//
//////////////////////////////////////////////////////////////////////////////////
module jupiter_ace (
module fpga_ace (
input wire clkram,
input wire clk65,
input wire clkcpu,

2
cores/JupiterAce/jupiter_ace.prj
View File

@ -10,4 +10,4 @@ verilog work "jace_logic.v"
verilog work "relojes.v"
verilog work "keyboard_for_ace.v"
verilog work "fpga_ace.v"
verilog work "tld_jace_spartan6.v"
verilog work "jupiter_ace.v"

4
cores/JupiterAce/jupiter_ace.v
View File

@ -19,7 +19,7 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tld_jace_spartan6 (
module jupiter_ace (
input wire clk50mhz,
input wire clkps2,
input wire dataps2,
@ -70,7 +70,7 @@ module tld_jace_spartan6 (
.CLK_OUT4() // Super CPU clock (just a test)
);
jupiter_ace the_core (
fpga_ace the_core (
.clkram(clkram),
.clk65(clk65),
.clkcpu(clkcpu),