mirror of https://github.com/zxdos/zxuno.git
Actualizo a última versión con los cambios de spark2k06 (botones select y start)
This commit is contained in:
antoniovillena
parent
164dc6d07f
commit
cd7c183a93
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@ -1,3 +1,3 @@
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End of code:\t000031f0 g *ABS* 00000000 _romend
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Start of BSS:\t000031f0 g .bss 00000000 __bss_start__
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End of BSS:\t00003728 g .bss 00000000 __bss_end__
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End of code:\t00001c08 g *ABS* 00000000 _romend
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Start of BSS:\t00001c08 g .bss 00000000 __bss_start__
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End of BSS:\t00002140 g .bss 00000000 __bss_end__
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File diff suppressed because it is too large
Load Diff
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@ -17,6 +17,7 @@
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#define HOST_CONTROL_SELECT 8
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#define HOST_CONTROL_START 16
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#define HOST_CONTROL_LOADER_RESET 32
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#define HOST_CONTROL_MASTER_RESET 64
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/* DIP switches / "Front Panel" controls - bits 15 downto 0 */
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#define REG_HOST_SCALERED 0x10
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@ -47,6 +47,8 @@
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#define KEY_1 0x16
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#define KEY_2 0x1E
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#define KEY_BACKSP 0x66
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int HandlePS2RawCodes();
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void ClearKeyboard();
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@ -44,6 +44,13 @@ void Delay()
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c--;
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}
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}
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void SuperDelay()
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{ int i=1;
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for (i=1;i<=576;i++)
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{
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Delay();
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}
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}
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void Reset(int row)
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{
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_RESET|HOST_CONTROL_DIVERT_KEYBOARD; // Reset host core
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@ -53,56 +60,8 @@ void Reset(int row)
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void Select(int row)
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{
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_SELECT|HOST_CONTROL_DIVERT_KEYBOARD; // Send select
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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SuperDelay();
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_DIVERT_KEYBOARD;
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}
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@ -110,54 +69,7 @@ void Start(int row)
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{
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_START|HOST_CONTROL_DIVERT_KEYBOARD; // Send start
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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SuperDelay();
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_DIVERT_KEYBOARD;
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}
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@ -165,54 +77,14 @@ void ResetLoader()
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{
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_LOADER_RESET;
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
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SuperDelay();
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}
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void masterReset()
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{
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HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_MASTER_RESET;
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SuperDelay();
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}
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static struct menu_entry topmenu[]; // Forward declaration.
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@ -152,6 +152,11 @@ int Menu_Run()
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if(TestKey(KEY_2))
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Select();
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// master reset
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if ((TestKey(KEY_LCTRL) || TestKey(KEY_RCTRL)) && (TestKey(KEY_ALT) || TestKey(KEY_ALTGR)) && TestKey(KEY_BACKSP) )
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{
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masterReset();
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}
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//q
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TestKey(KEY_PAGEUP);
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@ -160,6 +165,11 @@ int Menu_Run()
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return;
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}
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// master reset
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if ((TestKey(KEY_LCTRL) || TestKey(KEY_RCTRL)) && (TestKey(KEY_ALT) || TestKey(KEY_ALTGR)) && TestKey(KEY_BACKSP) )
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{
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masterReset();
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}
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if(TestKey(KEY_UPARROW)&2)
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{
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@ -45,6 +45,7 @@ entity CtrlModule is
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host_reset_loader : out std_logic;
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host_select : out std_logic;
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host_start : out std_logic;
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host_master_reset : out std_logic := '0';
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-- Boot upload signals
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host_bootdata : out std_logic_vector(31 downto 0);
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@ -326,6 +327,7 @@ begin
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host_select<=mem_write(3);
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host_start<=mem_write(4);
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host_reset_loader <=mem_write(5);
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host_master_reset <=mem_write(6);
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-- when X"F0" => -- Scale Red
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-- mem_busy<='0';
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@ -34,8 +34,9 @@ module GameLoader(input clk, input reset,
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reg [21:0] bytes_left;
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assign error = (state == 3);
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wire [7:0] prgrom = ines[4];
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wire [7:0] chrrom = ines[5];
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wire [7:0] prgrom = ines[4]; // Number of 16384 byte program ROM pages
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wire [7:0] chrrom = ines[5]; // Number of 8192 byte character ROM pages (0 indicates CHR RAM)
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wire has_chr_ram = (chrrom == 0);
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assign mem_data = indata;
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assign mem_write = (bytes_left != 0) && (state == 1 || state == 2) && indata_clk;
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@ -55,9 +56,25 @@ module GameLoader(input clk, input reset,
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chrrom <= 32 ? 5 :
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chrrom <= 64 ? 6 : 7;
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wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
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wire has_chr_ram = (chrrom == 0);
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assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
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// detect iNES2.0 compliant header
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wire is_nes20 = (ines[7][3:2] == 2'b10);
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// differentiate dirty iNES1.0 headers from proper iNES2.0 ones
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wire is_dirty = !is_nes20 && ((ines[8] != 0)
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|| (ines[9] != 0)
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|| (ines[10] != 0)
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|| (ines[11] != 0)
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|| (ines[12] != 0)
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|| (ines[13] != 0)
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|| (ines[14] != 0)
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|| (ines[15] != 0));
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// Read the mapper number
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wire [7:0] mapper = {is_dirty ? 4'b0000 : ines[7][7:4], ines[6][7:4]};
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// ines[6][0] is mirroring
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// ines[6][3] is 4 screen mode
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assign mapper_flags = {15'b0, ines[6][3], has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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@ -72,8 +89,8 @@ module GameLoader(input clk, input reset,
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ines[ctr] <= indata;
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bytes_left <= {prgrom, 14'b0};
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if (ctr == 4'b1111)
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state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] && !ines[6][3] ? 1 : 3;
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end
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// Check the 'NES' header. Also, we don't support trainers.
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state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] ? 1 : 3; end
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1, 2: begin // Read the next |bytes_left| bytes into |mem_addr|
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if (bytes_left != 0) begin
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if (indata_clk) begin
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@ -51,6 +51,8 @@ module NES_ZXUNO(
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wire host_select;
|
||||
wire host_start;
|
||||
|
||||
wire master_reset;
|
||||
|
||||
reg boot_state = 1'b0;
|
||||
|
||||
wire [31:0] bootdata;
|
||||
|
|
@ -127,8 +129,7 @@ module NES_ZXUNO(
|
|||
wire [7:0] joystick1, joystick2;
|
||||
wire p_sel = !host_select;
|
||||
wire p_start = !host_start;
|
||||
assign joystick1 = {~P_R, ~P_L, ~P_D, ~P_U, ~p_start, ~p_sel, ~P_tr, ~P_A};
|
||||
|
||||
assign joystick1 = {~P_R, ~P_L, ~P_D, ~P_U, ~p_start | (~P_R & ~P_L), ~p_sel | (~P_D & ~P_U), ~P_tr, ~P_A};
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (joypad_strobe) begin
|
||||
|
|
@ -276,7 +277,8 @@ wire [31:0] rom_size;
|
|||
.host_reset_loader(host_reset_loader),
|
||||
.host_bootdata(bootdata),
|
||||
.host_bootdata_req(bootdata_req),
|
||||
.host_bootdata_ack(bootdata_ack)
|
||||
.host_bootdata_ack(bootdata_ack),
|
||||
.host_master_reset(master_reset)
|
||||
);
|
||||
|
||||
OSD_Overlay osd (
|
||||
|
|
@ -385,4 +387,12 @@ begin
|
|||
loader_input <= dout_fifo;
|
||||
// data <= bytesloaded[19:4];
|
||||
end
|
||||
|
||||
//-----------------Multiboot-------------
|
||||
multiboot el_multiboot (
|
||||
.clk_icap(clk),
|
||||
.REBOOT(master_reset)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -212,9 +212,12 @@ module MMC2(input clk, input ce, input reset,
|
|||
end
|
||||
end
|
||||
|
||||
// Update latches when 0x3D8 or 0x3E8 is accessed.
|
||||
// PPU reads $0FD8: latch 0 is set to $FD for subsequent reads
|
||||
// PPU reads $0FE8: latch 0 is set to $FE for subsequent reads
|
||||
// PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
|
||||
// PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads
|
||||
always @(posedge clk) if (ce && chr_read) begin
|
||||
latch_0 <= (chr_ain & 14'h3ff8) == 14'h0fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h0fe8 ? 1 : latch_0;
|
||||
latch_0 <= (chr_ain & 14'h3fff) == 14'h0fd8 ? 0 : (chr_ain & 14'h3fff) == 14'h0fe8 ? 1 : latch_0;
|
||||
latch_1 <= (chr_ain & 14'h3ff8) == 14'h1fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h1fe8 ? 1 : latch_1;
|
||||
end
|
||||
|
||||
|
|
@ -248,8 +251,7 @@ module MMC2(input clk, input ce, input reset,
|
|||
assign chr_allow = flags[15];
|
||||
endmodule
|
||||
|
||||
|
||||
// This mapper also handles mapper 119 and 47.
|
||||
// This mapper also handles mapper 47,118,119 and 206.
|
||||
module MMC3(input clk, input ce, input reset,
|
||||
input [31:0] flags,
|
||||
input [15:0] prg_ain, output [21:0] prg_aout,
|
||||
|
|
@ -279,6 +281,9 @@ module MMC3(input clk, input ce, input reset,
|
|||
// TQROM maps 8kB CHR RAM
|
||||
wire TQROM = (flags[7:0] == 119);
|
||||
wire TxSROM = (flags[7:0] == 118); // Connects CHR A17 to CIRAM A10
|
||||
wire DxROM = (flags[7:0] == 206);
|
||||
|
||||
wire four_screen_mirroring = flags[16] | DxROM;
|
||||
|
||||
// Mapper 47 is a multicart that has 128k for each game. It has no RAM.
|
||||
wire mapper47 = (flags[7:0] == 47);
|
||||
|
|
@ -382,16 +387,144 @@ module MMC3(input clk, input ce, input reset,
|
|||
wire [21:0] prg_aout_tmp = {3'b00_0, prgsel, prg_ain[12:0]};
|
||||
|
||||
assign {chr_allow, chr_aout} =
|
||||
(TQROM && chrsel[6]) ? {1'b1, 9'b11_1111_111, chrsel[2:0], chr_ain[9:0]} : // TQROM 8kb CHR-RAM
|
||||
(TQROM && chrsel[6]) ? {1'b1, 9'b11_1111_111, chrsel[2:0], chr_ain[9:0]} : // TQROM 8kb CHR-RAM
|
||||
(four_screen_mirroring && chr_ain[13]) ? {1'b1, 9'b11_1111_111, chr_ain[13], chr_ain[11:0]} : // DxROM 8kb CHR-RAM
|
||||
{flags[15], 4'b10_00, chrsel, chr_ain[9:0]}; // Standard MMC3
|
||||
|
||||
assign prg_is_ram = prg_ain >= 'h6000 && prg_ain < 'h8000 && ram_enable && !(ram_protect && prg_write);
|
||||
assign prg_allow = prg_ain[15] && !prg_write || prg_is_ram && !mapper47;
|
||||
wire [21:0] prg_ram = {9'b11_1100_000, prg_ain[12:0]};
|
||||
assign prg_aout = prg_is_ram && !mapper47 ? prg_ram : prg_aout_tmp;
|
||||
assign prg_aout = prg_is_ram && !mapper47 && !DxROM ? prg_ram : prg_aout_tmp;
|
||||
assign vram_a10 = (TxSROM == 0) ? (mirroring ? chr_ain[11] : chr_ain[10]) :
|
||||
chrsel[7];
|
||||
assign vram_ce = chr_ain[13] && !four_screen_mirroring;
|
||||
endmodule
|
||||
|
||||
// MMC4 mapper chip. PRG ROM: 256kB. Bank Size: 16kB. CHR ROM: 128kB
|
||||
module MMC4(input clk, input ce, input reset,
|
||||
input [31:0] flags,
|
||||
input [15:0] prg_ain, output [21:0] prg_aout,
|
||||
input prg_read, prg_write, // Read / write signals
|
||||
input [7:0] prg_din,
|
||||
output prg_allow, // Enable access to memory for the specified operation.
|
||||
input chr_read, input [13:0] chr_ain, output [21:0] chr_aout,
|
||||
output chr_allow, // Allow write
|
||||
output vram_a10, // Value for A10 address line
|
||||
output vram_ce); // True if the address should be routed to the internal 2kB VRAM.
|
||||
|
||||
// PRG ROM bank select ($A000-$AFFF)
|
||||
// 7 bit 0
|
||||
// ---- ----
|
||||
// xxxx PPPP
|
||||
// ||||
|
||||
// ++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
|
||||
reg [3:0] prg_bank;
|
||||
|
||||
// CHR ROM $FD/0000 bank select ($B000-$BFFF)
|
||||
// 7 bit 0
|
||||
// ---- ----
|
||||
// xxxC CCCC
|
||||
// | ||||
|
||||
// +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
|
||||
// used when latch 0 = $FD
|
||||
reg [4:0] chr_bank_0a;
|
||||
|
||||
// CHR ROM $FE/0000 bank select ($C000-$CFFF)
|
||||
// 7 bit 0
|
||||
// ---- ----
|
||||
// xxxC CCCC
|
||||
// | ||||
|
||||
// +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
|
||||
// used when latch 0 = $FE
|
||||
reg [4:0] chr_bank_0b;
|
||||
|
||||
// CHR ROM $FD/1000 bank select ($D000-$DFFF)
|
||||
// 7 bit 0
|
||||
// ---- ----
|
||||
// xxxC CCCC
|
||||
// | ||||
|
||||
// +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
|
||||
// used when latch 1 = $FD
|
||||
reg [4:0] chr_bank_1a;
|
||||
|
||||
// CHR ROM $FE/1000 bank select ($E000-$EFFF)
|
||||
// 7 bit 0
|
||||
// ---- ----
|
||||
// xxxC CCCC
|
||||
// | ||||
|
||||
// +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
|
||||
// used when latch 1 = $FE
|
||||
reg [4:0] chr_bank_1b;
|
||||
|
||||
// Mirroring ($F000-$FFFF)
|
||||
// 7 bit 0
|
||||
// ---- ----
|
||||
// xxxx xxxM
|
||||
// |
|
||||
// +- Select nametable mirroring (0: vertical; 1: horizontal)
|
||||
reg mirroring;
|
||||
|
||||
reg latch_0, latch_1;
|
||||
|
||||
// Update registers
|
||||
always @(posedge clk) if (ce) begin
|
||||
if (reset)
|
||||
prg_bank <= 4'b1110;
|
||||
else if (prg_write && prg_ain[15]) begin
|
||||
case(prg_ain[14:12])
|
||||
2: prg_bank <= prg_din[3:0]; // $A000
|
||||
3: chr_bank_0a <= prg_din[4:0]; // $B000
|
||||
4: chr_bank_0b <= prg_din[4:0]; // $C000
|
||||
5: chr_bank_1a <= prg_din[4:0]; // $D000
|
||||
6: chr_bank_1b <= prg_din[4:0]; // $E000
|
||||
7: mirroring <= prg_din[0]; // $F000
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// PPU reads $0FD8 through $0FDF: latch 0 is set to $FD for subsequent reads
|
||||
// PPU reads $0FE8 through $0FEF: latch 0 is set to $FE for subsequent reads
|
||||
// PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
|
||||
// PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads
|
||||
always @(posedge clk) if (ce && chr_read) begin
|
||||
latch_0 <= (chr_ain & 14'h3ff8) == 14'h0fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h0fe8 ? 1 : latch_0;
|
||||
latch_1 <= (chr_ain & 14'h3ff8) == 14'h1fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h1fe8 ? 1 : latch_1;
|
||||
end
|
||||
|
||||
// The PRG bank to load. Each increment here is 16kb. So valid values are 0..15.
|
||||
reg [3:0] prgsel;
|
||||
always @* begin
|
||||
casez(prg_ain[14])
|
||||
1'b0: prgsel = prg_bank;
|
||||
default: prgsel = 4'b1111;
|
||||
endcase
|
||||
end
|
||||
wire [21:0] prg_aout_tmp = {4'b00_00, prgsel, prg_ain[13:0]};
|
||||
|
||||
// The CHR bank to load. Each increment here is 4kb. So valid values are 0..31.
|
||||
reg [4:0] chrsel;
|
||||
always @* begin
|
||||
casez({chr_ain[12], latch_0, latch_1})
|
||||
3'b00?: chrsel = chr_bank_0a;
|
||||
3'b01?: chrsel = chr_bank_0b;
|
||||
3'b1?0: chrsel = chr_bank_1a;
|
||||
3'b1?1: chrsel = chr_bank_1b;
|
||||
endcase
|
||||
end
|
||||
assign chr_aout = {5'b100_00, chrsel, chr_ain[11:0]};
|
||||
|
||||
// The a10 VRAM address line. (Used for mirroring)
|
||||
assign vram_a10 = mirroring ? chr_ain[11] : chr_ain[10];
|
||||
assign vram_ce = chr_ain[13];
|
||||
|
||||
assign chr_allow = flags[15];
|
||||
|
||||
wire prg_is_ram = prg_ain >= 'h6000 && prg_ain < 'h8000;
|
||||
assign prg_allow = prg_ain[15] && !prg_write ||
|
||||
prg_is_ram;
|
||||
wire [21:0] prg_ram = {9'b11_1100_000, prg_ain[12:0]};
|
||||
assign prg_aout = prg_is_ram ? prg_ram : prg_aout_tmp;
|
||||
|
||||
endmodule
|
||||
|
||||
module MMC5(input clk, input ce, input reset,
|
||||
|
|
@ -762,7 +895,7 @@ module Rambo1(input clk, input ce, input reset,
|
|||
{chr_bank_0, chr_bank_1} <= 0;
|
||||
{chr_bank_2, chr_bank_3, chr_bank_4, chr_bank_5} <= 0;
|
||||
{chr_bank_8, chr_bank_9} <= 0;
|
||||
{prg_bank_0, prg_bank_1, prg_bank_2} <= 0;
|
||||
{prg_bank_0, prg_bank_1, prg_bank_2} <= 6'b111111;
|
||||
irq_cycle_mode <= 0;
|
||||
cycle_counter <= 0;
|
||||
irq <= 0;
|
||||
|
|
@ -1592,6 +1725,11 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
|
|||
MMC3 mmc3(clk, ppu_ce, reset, flags, prg_ain, mmc3_prg_addr, prg_read, prg_write, prg_din, mmc3_prg_allow,
|
||||
chr_ain, mmc3_chr_addr, mmc3_chr_allow, mmc3_vram_a10, mmc3_vram_ce, mmc3_irq);
|
||||
|
||||
wire mmc4_prg_allow, mmc4_vram_a10, mmc4_vram_ce, mmc4_chr_allow;
|
||||
wire [21:0] mmc4_prg_addr, mmc4_chr_addr;
|
||||
MMC4 mmc4(clk, ppu_ce, reset, flags, prg_ain, mmc4_prg_addr, prg_read, prg_write, prg_din, mmc4_prg_allow,
|
||||
chr_read, chr_ain, mmc4_chr_addr, mmc4_chr_allow, mmc4_vram_a10, mmc4_vram_ce);
|
||||
|
||||
wire mmc5_prg_allow, mmc5_vram_a10, mmc5_vram_ce, mmc5_chr_allow, mmc5_irq;
|
||||
wire [21:0] mmc5_prg_addr, mmc5_chr_addr;
|
||||
wire [7:0] mmc5_chr_dout, mmc5_prg_dout;
|
||||
|
|
@ -1703,8 +1841,11 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
|
|||
118, // TxSROM connects A17 to CIRAM A10.
|
||||
119, // TQROM uses the Nintendo MMC3 like other TxROM boards but uses the CHR bank number specially.
|
||||
47, // Mapper 047 is a MMC3 multicart
|
||||
206, // MMC3 w/o IRQ or WRAM support
|
||||
4: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow, irq} = {mmc3_prg_addr, mmc3_prg_allow, mmc3_chr_addr, mmc3_vram_a10, mmc3_vram_ce, mmc3_chr_allow, mmc3_irq};
|
||||
|
||||
10: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow} = {mmc4_prg_addr, mmc4_prg_allow, mmc4_chr_addr, mmc4_vram_a10, mmc4_vram_ce, mmc4_chr_allow};
|
||||
|
||||
5: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow, has_chr_dout, prg_dout, irq} = {mmc5_prg_addr, mmc5_prg_allow, mmc5_chr_addr, mmc5_vram_a10, mmc5_vram_ce, mmc5_chr_allow, mmc5_has_chr_dout, mmc5_prg_dout, mmc5_irq};
|
||||
|
||||
0,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,310 @@
|
|||
module multiboot (
|
||||
input wire clk_icap,
|
||||
input wire REBOOT
|
||||
);
|
||||
|
||||
reg [23:0] spi_addr = 24'h058000; // default: SPI address of second core as defined by the SPI memory map
|
||||
|
||||
reg [4:0] q = 5'b00000;
|
||||
reg reboot_ff = 1'b0;
|
||||
|
||||
always @(posedge clk_icap) begin
|
||||
q[0] <= REBOOT;
|
||||
q[1] <= q[0];
|
||||
q[2] <= q[1];
|
||||
q[3] <= q[2];
|
||||
q[4] <= q[3];
|
||||
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
|
||||
end
|
||||
|
||||
multiboot_spartan6 hacer_multiboot (
|
||||
.CLK(clk_icap),
|
||||
.MBT_RESET(1'b0),
|
||||
.MBT_REBOOT(reboot_ff),
|
||||
.spi_addr(spi_addr)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module multiboot_spartan6 (
|
||||
input wire CLK,
|
||||
input wire MBT_RESET,
|
||||
input wire MBT_REBOOT,
|
||||
input wire [23:0] spi_addr
|
||||
);
|
||||
|
||||
reg [15:0] icap_din;
|
||||
reg icap_ce;
|
||||
reg icap_wr;
|
||||
|
||||
reg [15:0] ff_icap_din_reversed;
|
||||
reg ff_icap_ce;
|
||||
reg ff_icap_wr;
|
||||
|
||||
|
||||
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
|
||||
|
||||
.CE (ff_icap_ce), // Clock enable input
|
||||
.CLK (CLK), // Clock input
|
||||
.I (ff_icap_din_reversed), // 16-bit data input
|
||||
.WRITE (ff_icap_wr) // Write input
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------
|
||||
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
|
||||
// -------------------------------------------------
|
||||
|
||||
|
||||
parameter IDLE = 0,
|
||||
SYNC_H = 1,
|
||||
SYNC_L = 2,
|
||||
|
||||
CWD_H = 3,
|
||||
CWD_L = 4,
|
||||
|
||||
GEN1_H = 5,
|
||||
GEN1_L = 6,
|
||||
|
||||
GEN2_H = 7,
|
||||
GEN2_L = 8,
|
||||
|
||||
GEN3_H = 9,
|
||||
GEN3_L = 10,
|
||||
|
||||
GEN4_H = 11,
|
||||
GEN4_L = 12,
|
||||
|
||||
GEN5_H = 13,
|
||||
GEN5_L = 14,
|
||||
|
||||
NUL_H = 15,
|
||||
NUL_L = 16,
|
||||
|
||||
MOD_H = 17,
|
||||
MOD_L = 18,
|
||||
|
||||
HCO_H = 19,
|
||||
HCO_L = 20,
|
||||
|
||||
RBT_H = 21,
|
||||
RBT_L = 22,
|
||||
|
||||
NOOP_0 = 23,
|
||||
NOOP_1 = 24,
|
||||
NOOP_2 = 25,
|
||||
NOOP_3 = 26;
|
||||
|
||||
|
||||
reg [4:0] state;
|
||||
reg [4:0] next_state;
|
||||
|
||||
|
||||
always @*
|
||||
begin: COMB
|
||||
|
||||
case (state)
|
||||
|
||||
IDLE:
|
||||
begin
|
||||
if (MBT_REBOOT)
|
||||
begin
|
||||
next_state = SYNC_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'hAA99; // Sync word 1
|
||||
end
|
||||
else
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'hFFFF; // Null
|
||||
end
|
||||
end
|
||||
|
||||
SYNC_H:
|
||||
begin
|
||||
next_state = SYNC_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h5566; // Sync word 2
|
||||
end
|
||||
|
||||
SYNC_L:
|
||||
begin
|
||||
next_state = NUL_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
NUL_H:
|
||||
begin
|
||||
// next_state = NUL_L;
|
||||
next_state = GEN1_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
|
||||
end
|
||||
|
||||
//Q
|
||||
|
||||
GEN1_H:
|
||||
begin
|
||||
next_state = GEN1_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
|
||||
end
|
||||
|
||||
GEN1_L:
|
||||
begin
|
||||
next_state = GEN2_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
|
||||
end
|
||||
|
||||
GEN2_H:
|
||||
begin
|
||||
next_state = GEN2_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3281; // Escritura a reg GENERAL_2
|
||||
end
|
||||
|
||||
GEN2_L:
|
||||
begin
|
||||
next_state = MOD_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
|
||||
end
|
||||
|
||||
/////// Registro MODE (para carga a 4x tras reboot)
|
||||
|
||||
MOD_H:
|
||||
begin
|
||||
next_state = MOD_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3301; // Escritura a reg MODE
|
||||
end
|
||||
|
||||
MOD_L:
|
||||
begin
|
||||
next_state = NUL_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
|
||||
end
|
||||
/////
|
||||
|
||||
NUL_L:
|
||||
begin
|
||||
next_state = RBT_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
RBT_H:
|
||||
begin
|
||||
next_state = RBT_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h000E; // REBOOT Command 0x000E
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
RBT_L:
|
||||
begin
|
||||
next_state = NOOP_0;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_0:
|
||||
begin
|
||||
next_state = NOOP_1;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_1:
|
||||
begin
|
||||
next_state = NOOP_2;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_2:
|
||||
begin
|
||||
next_state = NOOP_3;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
NOOP_3:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // NULL value
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // 16'h1111"
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: SEQ
|
||||
if (MBT_RESET)
|
||||
state <= IDLE;
|
||||
else
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: ICAP_FF
|
||||
|
||||
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
|
||||
ff_icap_din_reversed[1] <= icap_din[6];
|
||||
ff_icap_din_reversed[2] <= icap_din[5];
|
||||
ff_icap_din_reversed[3] <= icap_din[4];
|
||||
ff_icap_din_reversed[4] <= icap_din[3];
|
||||
ff_icap_din_reversed[5] <= icap_din[2];
|
||||
ff_icap_din_reversed[6] <= icap_din[1];
|
||||
ff_icap_din_reversed[7] <= icap_din[0];
|
||||
ff_icap_din_reversed[8] <= icap_din[15];
|
||||
ff_icap_din_reversed[9] <= icap_din[14];
|
||||
ff_icap_din_reversed[10] <= icap_din[13];
|
||||
ff_icap_din_reversed[11] <= icap_din[12];
|
||||
ff_icap_din_reversed[12] <= icap_din[11];
|
||||
ff_icap_din_reversed[13] <= icap_din[10];
|
||||
ff_icap_din_reversed[14] <= icap_din[9];
|
||||
ff_icap_din_reversed[15] <= icap_din[8];
|
||||
|
||||
ff_icap_ce <= icap_ce;
|
||||
ff_icap_wr <= icap_wr;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -15,6 +15,7 @@ vhdl work "../src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd"
|
|||
verilog work "../src/vga.v"
|
||||
verilog work "../src/sigma_delta_dac.v"
|
||||
verilog work "../src/nes.v"
|
||||
verilog work "../src/multiboot_v4.v"
|
||||
verilog work "../src/memorycontroller.v"
|
||||
verilog work "../src/hq2x.v"
|
||||
verilog work "../src/GameLoader.v"
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ run
|
|||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-uc "timings.xcf"
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
# Timing constraints
|
||||
NET "CLOCK_50" PERIOD=20 ns;
|
||||
Loading…
Reference in New Issue