mirror of https://github.com/zxdos/zxuno.git
Spectrum test20 (última versión)
This commit is contained in:
antoniovillena
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@ -0,0 +1,78 @@
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`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:24:57 12/06/2015
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// Design Name:
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// Module Name: control_rasterint
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rasterint_ctrl (
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output reg oe_n,
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output wire rasterint_enable,
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output wire vretraceint_disable,
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output wire [8:0] raster_line,
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input wire raster_int_in_progress
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);
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parameter RASTERLINE = 8'h0C;
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parameter RASTERCTRL = 8'h0D;
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reg [7:0] rasterline_reg = 8'hFF;
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reg raster_enable = 1'b0;
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reg vretrace_disable = 1'b0;
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reg raster_8th_bit = 1'b1;
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assign raster_line = {raster_8th_bit, rasterline_reg};
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assign rasterint_enable = raster_enable;
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assign vretraceint_disable = vretrace_disable;
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always @(posedge clk) begin
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if (rst_n == 1'b0) begin
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raster_enable <= 1'b0;
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vretrace_disable <= 1'b0;
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raster_8th_bit <= 1'b1;
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rasterline_reg <= 8'hFF;
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end
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else begin
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if (zxuno_addr == RASTERLINE && zxuno_regwr == 1'b1)
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rasterline_reg <= din;
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if (zxuno_addr == RASTERCTRL && zxuno_regwr == 1'b1)
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{vretrace_disable, raster_enable, raster_8th_bit} <= din[2:0];
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end
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end
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always @* begin
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dout = 8'hFF;
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oe_n = 1'b1;
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if (zxuno_addr == RASTERLINE && zxuno_regrd == 1'b1) begin
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dout = rasterline_reg;
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oe_n = 1'b0;
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end
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if (zxuno_addr == RASTERCTRL && zxuno_regrd == 1'b1) begin
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dout = {raster_int_in_progress, 4'b0000, vretrace_disable, raster_enable, raster_8th_bit};
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oe_n = 1'b0;
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end
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end
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endmodule
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@ -36,13 +36,13 @@ module coreid (
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for (i=0;i<16;i=i+1)
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text[i] = 8'h00;
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text[ 0] = "T";
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text[ 1] = "1";
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text[ 2] = "9";
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text[ 1] = "2";
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text[ 2] = "0";
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text[ 3] = "-";
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text[ 4] = "0";
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text[ 5] = "3";
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text[ 5] = "7";
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text[ 6] = "1";
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text[ 7] = "0";
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text[ 7] = "2";
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text[ 8] = "2";
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text[ 9] = "0";
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text[10] = "1";
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@ -1,162 +1,74 @@
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// file: tres_relojes.v
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//
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// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
|
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// international copyright and other intellectual property
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// laws.
|
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
|
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
|
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// Xilinx, and to the maximum extent permitted by applicable
|
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
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//
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// CRITICAL APPLICATIONS
|
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// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
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// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
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// PART OF THIS FILE AT ALL TIMES.
|
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//
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//----------------------------------------------------------------------------
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// User entered comments
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//----------------------------------------------------------------------------
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// None
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//
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//----------------------------------------------------------------------------
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// Output Output Phase Duty Cycle Pk-to-Pk Phase
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// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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//----------------------------------------------------------------------------
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// CLK_OUT1 28.000 0.000 50.0 297.991 199.399
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// CLK_OUT2 14.000 180.000 50.0 342.124 199.399
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// CLK_OUT3 7.000 180.000 50.0 391.159 199.399
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//
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//----------------------------------------------------------------------------
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// Input Clock Input Freq (MHz) Input Jitter (UI)
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//----------------------------------------------------------------------------
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// primary 50 0.010
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`timescale 1ps/1ps
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`default_nettype none
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(* CORE_GENERATION_INFO = "tres_relojes,clk_wiz_v1_8,{component_name=tres_relojes,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
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module cuatro_relojes
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/* Change parameters using this online C code: http://goo.gl/Os0cKi */
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module clock_generator
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(// Clock in ports
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input wire CLK_IN1,
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input wire CPUContention,
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input wire [2:0] pll_option,
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input wire turbo_enable,
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// Clock out ports
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output wire CLK_OUT1,
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output wire CLK_OUT2,
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output wire CLK_OUT3,
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output wire CLK_OUT4
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);
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output wire CLK_OUT4,
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output wire cpuclk
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);
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wire cpuclk_selected;
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reg [2:0] pll_option_stored = 3'b000;
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reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot
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always @(posedge CLK_IN1) begin
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if (pll_option != pll_option_stored) begin
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pll_option_stored <= pll_option;
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pulso_reconf <= 8'b00000001;
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end
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else begin
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pulso_reconf <= {pulso_reconf[6:0],1'b0};
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end
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end
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wire clkin1,clkout0,clkout1,clkout2,clkout3;
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// Input buffering
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//------------------------------------
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IBUFG clkin1_buf
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(.O (clkin1),
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.I (CLK_IN1));
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pll_top reconfiguracion_pll
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(
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// SSTEP is the input to start a reconfiguration. It should only be
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// pulsed for one clock cycle.
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.SSTEP(pulso_reconf[7]),
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// STATE determines which state the PLL_ADV will be reconfigured to. A
|
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// value of 0 correlates to state 1, and a value of 1 correlates to state
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// 2.
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.STATE(pll_option_stored),
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// RST will reset the entire reference design including the PLL_ADV
|
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.RST(1'b0),
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// CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the
|
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// clock for the PLL_DRP module
|
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.CLKIN(CLK_IN1),
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// SRDY pulses for one clock cycle after the PLL_ADV is locked and the
|
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// PLL_DRP module is ready to start another re-configuration
|
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.SRDY(),
|
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// These are the clock outputs from the PLL_ADV.
|
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.CLK0OUT(CLK_OUT1),
|
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.CLK1OUT(CLK_OUT2),
|
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.CLK2OUT(CLK_OUT3),
|
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.CLK3OUT(CLK_OUT4)
|
||||
);
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||||
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// Clocking primitive
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//------------------------------------
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// Instantiation of the PLL primitive
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire [15:0] do_unused;
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wire drdy_unused;
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wire locked_unused;
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wire clkfbout;
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wire clkfbout_buf;
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wire clkout4_unused;
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wire clkout5_unused;
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PLL_BASE
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#(.BANDWIDTH ("OPTIMIZED"),
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.CLK_FEEDBACK ("CLKFBOUT"),
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.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
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.DIVCLK_DIVIDE (1),
|
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.CLKFBOUT_MULT (9),
|
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.CLKFBOUT_PHASE (0.000),
|
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.CLKOUT0_DIVIDE (16),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
|
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.CLKOUT1_DIVIDE (32),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT2_DIVIDE (64),
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.CLKOUT2_PHASE (0.000),
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.CLKOUT3_DIVIDE (128),
|
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.CLKOUT3_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKIN_PERIOD (20.0),
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.REF_JITTER (0.010))
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pll_base_inst
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// Output clocks
|
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(.CLKFBOUT (clkfbout),
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.CLKOUT0 (clkout0),
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.CLKOUT1 (clkout1),
|
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.CLKOUT2 (clkout2),
|
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.CLKOUT3 (clkout3),
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.CLKOUT4 (clkout4_unused),
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.CLKOUT5 (clkout5_unused),
|
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.LOCKED (locked_unused),
|
||||
.RST (1'b0),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf),
|
||||
.CLKIN (clkin1));
|
||||
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf),
|
||||
.I (clkfbout));
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (CLK_OUT1),
|
||||
.I (clkout0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CLK_OUT2),
|
||||
.I (clkout1));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (CLK_OUT3),
|
||||
.I (clkout2));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (CLK_OUT4),
|
||||
.I (clkout3));
|
||||
BUFGMUX cpuclk_selector (
|
||||
.O(cpuclk_selected),
|
||||
.I0(CLK_OUT4),
|
||||
.I1(CLK_OUT3),
|
||||
.S(turbo_enable)
|
||||
);
|
||||
|
||||
BUFGMUX selector_reloj_cpu (
|
||||
.O(cpuclk),
|
||||
.I0(cpuclk_selected), // when no contention, clock is this one
|
||||
.I1(1'b1), // during contention, clock is pulled up
|
||||
.S(CPUContention) // contention signal
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,432 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
typedef unsigned char BYTE;
|
||||
/*
|
||||
8 8 3 5 3 5
|
||||
AAADDDDD AAADDDDD MRN JJJJJ MMM XXXXX
|
||||
|
||||
AAA = semifila del teclado a modificar | esta información está
|
||||
DDDDD = dato (AND negado con lo que haya) de esa semifila | repetida para dos teclas
|
||||
MRN = Master reset, Reset de usuario, NMI
|
||||
JJJJJ = estado del joystick al pulsar tecla. Posiciones UDLRX
|
||||
MMM = la tecla es un modificador
|
||||
XXXXX = Reservado para uso futuro
|
||||
|
||||
Ej: en la dirección de memoria correspondiente al código de la tecla ESC,
|
||||
que correspondería a la pulsación simultánea de CAPS SHIFT+SPACE, pondríamos:
|
||||
00000001 11100001 000 00000 000 00000
|
||||
Esto es: se activan las semifilas 0 y 7, y en cada una, se activa el bit 0
|
||||
|
||||
256 codigos + E0 = 512 codigos
|
||||
SHIFT, CTRL, ALT = 8 combinaciones
|
||||
|
||||
512*8=4096 direcciones x 32 bits = 16384 bytes
|
||||
En el core se dispondrá como una memoria de 16384x8 bits
|
||||
|
||||
Cada tecla ocupará cuatro direcciones consecutivas.
|
||||
D+0 : tecla1 (o 0 si no la hay)
|
||||
D+1 : tecla2 (o 0 si no la hay)
|
||||
D+2 : señales de reset y joystick, 0 si no hay
|
||||
D+3 : modificadores y señales de usuario, 0 si no hay
|
||||
*/
|
||||
|
||||
// You shouldn't have to touch these defs unless your Spectrum has a different keyboard
|
||||
// layout (because, for example, you are using a different ROM
|
||||
|
||||
#define SP_1 0x61
|
||||
#define SP_2 0x62
|
||||
#define SP_3 0x64
|
||||
#define SP_4 0x68
|
||||
#define SP_5 0x70
|
||||
|
||||
#define SP_0 0x81
|
||||
#define SP_9 0x82
|
||||
#define SP_8 0x84
|
||||
#define SP_7 0x88
|
||||
#define SP_6 0x90
|
||||
|
||||
#define SP_Q 0x41
|
||||
#define SP_W 0x42
|
||||
#define SP_E 0x44
|
||||
#define SP_R 0x48
|
||||
#define SP_T 0x50
|
||||
|
||||
#define SP_P 0xA1
|
||||
#define SP_O 0xA2
|
||||
#define SP_I 0xA4
|
||||
#define SP_U 0xA8
|
||||
#define SP_Y 0xB0
|
||||
|
||||
#define SP_A 0x21
|
||||
#define SP_S 0x22
|
||||
#define SP_D 0x24
|
||||
#define SP_F 0x28
|
||||
#define SP_G 0x30
|
||||
|
||||
#define SP_ENTER 0xC1
|
||||
#define SP_L 0xC2
|
||||
#define SP_K 0xC4
|
||||
#define SP_J 0xC8
|
||||
#define SP_H 0xD0
|
||||
|
||||
#define SP_CAPS 0x01
|
||||
#define SP_Z 0x02
|
||||
#define SP_X 0x04
|
||||
#define SP_C 0x08
|
||||
#define SP_V 0x10
|
||||
|
||||
#define SP_SPACE 0xE1
|
||||
#define SP_SYMBOL 0xE2
|
||||
#define SP_M 0xE4
|
||||
#define SP_N 0xE8
|
||||
#define SP_B 0xF0
|
||||
|
||||
#define SP_BANG (SP_SYMBOL<<8) | SP_1
|
||||
#define SP_AT (SP_SYMBOL<<8) | SP_2
|
||||
#define SP_HASH (SP_SYMBOL<<8) | SP_3
|
||||
#define SP_DOLLAR (SP_SYMBOL<<8) | SP_4
|
||||
#define SP_PERCEN (SP_SYMBOL<<8) | SP_5
|
||||
#define SP_AMP (SP_SYMBOL<<8) | SP_6
|
||||
#define SP_APOSTRO (SP_SYMBOL<<8) | SP_7
|
||||
#define SP_PAROPEN (SP_SYMBOL<<8) | SP_8
|
||||
#define SP_PARCLOS (SP_SYMBOL<<8) | SP_9
|
||||
#define SP_UNDERSC (SP_SYMBOL<<8) | SP_0
|
||||
#define SP_LESS (SP_SYMBOL<<8) | SP_R
|
||||
#define SP_LESSEQ (SP_SYMBOL<<8) | SP_Q
|
||||
#define SP_GREATER (SP_SYMBOL<<8) | SP_T
|
||||
#define SP_GREATEQ (SP_SYMBOL<<8) | SP_E
|
||||
#define SP_NOTEQ (SP_SYMBOL<<8) | SP_W
|
||||
#define SP_BRAOPEN (SP_SYMBOL<<8) | SP_Y
|
||||
#define SP_BRACLOS (SP_SYMBOL<<8) | SP_U
|
||||
#define SP_SEMICOL (SP_SYMBOL<<8) | SP_O
|
||||
#define SP_QUOTE (SP_SYMBOL<<8) | SP_P
|
||||
#define SP_TILDE (SP_SYMBOL<<8) | SP_A
|
||||
#define SP_PIPE (SP_SYMBOL<<8) | SP_S
|
||||
#define SP_BACKSLA (SP_SYMBOL<<8) | SP_D
|
||||
#define SP_CUROPEN (SP_SYMBOL<<8) | SP_F
|
||||
#define SP_CURCLOS (SP_SYMBOL<<8) | SP_G
|
||||
#define SP_CARET (SP_SYMBOL<<8) | SP_H
|
||||
#define SP_MINUS (SP_SYMBOL<<8) | SP_J
|
||||
#define SP_PLUS (SP_SYMBOL<<8) | SP_K
|
||||
#define SP_EQUAL (SP_SYMBOL<<8) | SP_L
|
||||
#define SP_COLON (SP_SYMBOL<<8) | SP_Z
|
||||
#define SP_POUND (SP_SYMBOL<<8) | SP_X
|
||||
#define SP_QUEST (SP_SYMBOL<<8) | SP_C
|
||||
#define SP_SLASH (SP_SYMBOL<<8) | SP_V
|
||||
#define SP_STAR (SP_SYMBOL<<8) | SP_B
|
||||
#define SP_COMMA (SP_SYMBOL<<8) | SP_N
|
||||
#define SP_DOT (SP_SYMBOL<<8) | SP_M
|
||||
|
||||
#define SP_EXTEND (SP_CAPS<<8) | SP_SYMBOL
|
||||
#define SP_EDIT (SP_CAPS<<8) | SP_1
|
||||
#define SP_CPSLOCK (SP_CAPS<<8) | SP_2
|
||||
#define SP_TRUE (SP_CAPS<<8) | SP_3
|
||||
#define SP_INVERSE (SP_CAPS<<8) | SP_4
|
||||
#define SP_LEFT (SP_CAPS<<8) | SP_5
|
||||
#define SP_DOWN (SP_CAPS<<8) | SP_6
|
||||
#define SP_UP (SP_CAPS<<8) | SP_7
|
||||
#define SP_RIGHT (SP_CAPS<<8) | SP_8
|
||||
#define SP_GRAPH (SP_CAPS<<8) | SP_9
|
||||
#define SP_DELETE (SP_CAPS<<8) | SP_0
|
||||
#define SP_BREAK (SP_CAPS<<8) | SP_SPACE
|
||||
|
||||
// END of Spectrum keys definitions
|
||||
|
||||
// Definitions for additional signals generated by the keyboard core
|
||||
// AAADDDDD AAADDDDD MRN JJJJJ MMM XXXXX
|
||||
#define MODIFIER1 0x20
|
||||
#define MODIFIER2 0x40
|
||||
#define MODIFIER3 0x80
|
||||
|
||||
#define MRESET 0x80
|
||||
#define URESET 0x40
|
||||
#define NMI 0x20
|
||||
|
||||
#define JOYUP 0x10
|
||||
#define JOYDOWN 0x08
|
||||
#define JOYLEFT 0x04
|
||||
#define JOYRIGHT 0x02
|
||||
#define JOYFIRE 0x01
|
||||
|
||||
#define USER5 0x10
|
||||
#define USER4 0x08
|
||||
#define USER3 0x04
|
||||
#define USER2 0x02
|
||||
#define USER1 0x01
|
||||
// End of additional signals
|
||||
|
||||
// A key can be pressed with up to three key modifiers
|
||||
// which generates 8 combinations for each key
|
||||
#define EXT 0x100
|
||||
#define MD1 0x200
|
||||
#define MD2 0x400
|
||||
#define MD3 0x800
|
||||
|
||||
// Scan code 2 list. First, non localized keys
|
||||
#define PC_A 0x1C
|
||||
#define PC_B 0x32
|
||||
#define PC_C 0x21
|
||||
#define PC_D 0x23
|
||||
#define PC_E 0x24
|
||||
#define PC_F 0x2B
|
||||
#define PC_G 0x34
|
||||
#define PC_H 0x33
|
||||
#define PC_I 0x43
|
||||
#define PC_J 0x3B
|
||||
#define PC_K 0x42
|
||||
#define PC_L 0x4B
|
||||
#define PC_M 0x3A
|
||||
#define PC_N 0x31
|
||||
#define PC_O 0x44
|
||||
#define PC_P 0x4D
|
||||
#define PC_Q 0x15
|
||||
#define PC_R 0x2D
|
||||
#define PC_S 0x1B
|
||||
#define PC_T 0x2C
|
||||
#define PC_U 0x3C
|
||||
#define PC_V 0x2A
|
||||
#define PC_W 0x1D
|
||||
#define PC_X 0x22
|
||||
#define PC_Y 0x35
|
||||
#define PC_Z 0x1A
|
||||
|
||||
#define PC_0 0x45
|
||||
#define PC_1 0x16
|
||||
#define PC_2 0x1E
|
||||
#define PC_3 0x26
|
||||
#define PC_4 0x25
|
||||
#define PC_5 0x2E
|
||||
#define PC_6 0x36
|
||||
#define PC_7 0x3D
|
||||
#define PC_8 0x3E
|
||||
#define PC_9 0x46
|
||||
|
||||
#define PC_F1 0x05
|
||||
#define PC_F2 0x06
|
||||
#define PC_F3 0x04
|
||||
#define PC_F4 0x0C
|
||||
#define PC_F5 0x03
|
||||
#define PC_F6 0x0B
|
||||
#define PC_F7 0x83
|
||||
#define PC_F8 0x0A
|
||||
#define PC_F9 0x01
|
||||
#define PC_F10 0x09
|
||||
#define PC_F11 0x78
|
||||
#define PC_F12 0x07
|
||||
|
||||
#define PC_ESC 0x76
|
||||
#define PC_SPACE 0x29
|
||||
#define PC_LCTRL 0x14
|
||||
#define PC_RCTRL 0x14 | EXT
|
||||
#define PC_LSHIFT 0x12
|
||||
#define PC_RSHIFT 0x59
|
||||
#define PC_LALT 0x11
|
||||
#define PC_RALT 0x11 | EXT
|
||||
#define PC_LWIN 0x1F | EXT
|
||||
#define PC_RWIN 0x27 | EXT
|
||||
#define PC_APPS 0x2F | EXT
|
||||
|
||||
#define PC_TAB 0x0D
|
||||
#define PC_CPSLOCK 0x58
|
||||
#define PC_SCRLOCK 0x7E
|
||||
|
||||
#define PC_INSERT 0x70 | EXT
|
||||
#define PC_DELETE 0x71 | EXT
|
||||
#define PC_HOME 0x6C | EXT
|
||||
#define PC_END 0x69 | EXT
|
||||
#define PC_PGUP 0x7D | EXT
|
||||
#define PC_PGDOWN 0x7A | EXT
|
||||
#define PC_BKSPACE 0x66
|
||||
#define PC_ENTER 0x5A
|
||||
#define PC_UP 0x75 | EXT
|
||||
#define PC_DOWN 0x72 | EXT
|
||||
#define PC_LEFT 0x6B | EXT
|
||||
#define PC_RIGHT 0x74 | EXT
|
||||
|
||||
#define PC_NUMLOCK 0x77
|
||||
#define PC_KP_DIVIS 0x4A | EXT
|
||||
#define PC_KP_MULT 0x7C
|
||||
#define PC_KP_MINUS 0x7B
|
||||
#define PC_KP_PLUS 0x79
|
||||
#define PC_KP_ENTER 0x5A | EXT
|
||||
#define PC_KP_DOT 0x71
|
||||
#define PC_KP_0 0x70
|
||||
#define PC_KP_1 0x69
|
||||
#define PC_KP_2 0x72
|
||||
#define PC_KP_3 0x7A
|
||||
#define PC_KP_4 0x6B
|
||||
#define PC_KP_5 0x73
|
||||
#define PC_KP_6 0x74
|
||||
#define PC_KP_7 0x6C
|
||||
#define PC_KP_8 0x75
|
||||
#define PC_KP_9 0x7D
|
||||
|
||||
// Localized keyboards start to differenciate from here
|
||||
|
||||
// Localized keyboard ES (Spain)
|
||||
#define PC_BACKSLA 0x0E
|
||||
#define PC_APOSTRO 0x4E
|
||||
#define PC_OPNBANG 0x55
|
||||
#define PC_GRAVEAC 0x54
|
||||
#define PC_PLUS 0x5B
|
||||
#define PC_EGNE 0x4C
|
||||
#define PC_ACUTEAC 0x52
|
||||
#define PC_CEDILLA 0x5D
|
||||
#define PC_LESS 0x61
|
||||
#define PC_COMMA 0x41
|
||||
#define PC_DOT 0x49
|
||||
#define PC_MINUS 0x4A
|
||||
|
||||
#define MAP(pc,sp,rj,mu) { \
|
||||
rom[(pc)*4] = (((sp)>>8)&0xFF); \
|
||||
rom[(pc)*4+1] = (((sp))&0xFF); \
|
||||
rom[(pc)*4+2] = (rj); \
|
||||
rom[(pc)*4+3] = (mu); \
|
||||
}
|
||||
|
||||
#define MAPANY(pc,sp,rj,mu) { \
|
||||
MAP(pc,sp,rj,mu); \
|
||||
MAP(MD1|pc,sp,rj,mu); \
|
||||
MAP(MD2|pc,sp,rj,mu); \
|
||||
MAP(MD3|pc,sp,rj,mu); \
|
||||
MAP(MD1|MD2|pc,sp,rj,mu); \
|
||||
MAP(MD1|MD3|pc,sp,rj,mu); \
|
||||
MAP(MD2|MD3|pc,sp,rj,mu); \
|
||||
MAP(MD1|MD2|MD3|pc,sp,rj,mu); \
|
||||
}
|
||||
|
||||
#define CLEANMAP { \
|
||||
int i; \
|
||||
for (i=0;i<(sizeof(rom)/sizeof(rom[0]));i++) \
|
||||
rom[i] = 0; \
|
||||
}
|
||||
#define SAVEMAPHEX(name) { \
|
||||
FILE *f; \
|
||||
int i; \
|
||||
f=fopen(name,"w"); \
|
||||
for(i=0;i<(sizeof(rom)/sizeof(rom[0]));i++) \
|
||||
fprintf(f,"%.2X\n",rom[i]); \
|
||||
fclose(f); \
|
||||
}
|
||||
|
||||
#define SAVEMAPBIN(name) { \
|
||||
FILE *f; \
|
||||
int i; \
|
||||
f=fopen(name,"wb"); \
|
||||
fwrite (rom, 1, sizeof(rom), f); \
|
||||
fclose(f); \
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
BYTE rom[16384];
|
||||
|
||||
CLEANMAP;
|
||||
|
||||
MAPANY(PC_LSHIFT,SP_CAPS,0,0);
|
||||
MAPANY(PC_RSHIFT,SP_CAPS,0,0);
|
||||
MAPANY(PC_LCTRL,SP_SYMBOL,0,MODIFIER2); // MD2 is CTRL
|
||||
MAPANY(PC_RCTRL,SP_SYMBOL,0,MODIFIER2); // MD2 is CTRL
|
||||
MAPANY(PC_LALT,0,JOYFIRE,MODIFIER3); // MD3 is ALT. Also is FIRE for keyboard joystick
|
||||
MAPANY(PC_RALT,0,JOYFIRE,MODIFIER3); // MD3 is ALT. Also is FIRE for keyboard joystick
|
||||
|
||||
// Basic mapping: each key from PC is mapped to a key in the Spectrum
|
||||
MAPANY(PC_1,SP_1,0,0);
|
||||
MAPANY(PC_2,SP_2,0,0);
|
||||
MAPANY(PC_3,SP_3,0,0);
|
||||
MAPANY(PC_4,SP_4,0,0);
|
||||
MAPANY(PC_5,SP_5,0,0);
|
||||
MAPANY(PC_6,SP_6,0,0);
|
||||
MAPANY(PC_7,SP_7,0,0);
|
||||
MAPANY(PC_8,SP_8,0,0);
|
||||
MAPANY(PC_9,SP_9,0,0);
|
||||
MAPANY(PC_0,SP_0,0,0);
|
||||
|
||||
MAPANY(PC_Q,SP_Q,0,0);
|
||||
MAPANY(PC_W,SP_W,0,0);
|
||||
MAPANY(PC_E,SP_E,0,0);
|
||||
MAPANY(PC_R,SP_R,0,0);
|
||||
MAPANY(PC_T,SP_T,0,0);
|
||||
MAPANY(PC_Y,SP_Y,0,0);
|
||||
MAPANY(PC_U,SP_U,0,0);
|
||||
MAPANY(PC_I,SP_I,0,0);
|
||||
MAPANY(PC_O,SP_O,0,0);
|
||||
MAPANY(PC_P,SP_P,0,0);
|
||||
MAPANY(PC_A,SP_A,0,0);
|
||||
MAPANY(PC_S,SP_S,0,0);
|
||||
MAPANY(PC_D,SP_D,0,0);
|
||||
MAPANY(PC_F,SP_F,0,0);
|
||||
MAPANY(PC_G,SP_G,0,0);
|
||||
MAPANY(PC_H,SP_H,0,0);
|
||||
MAPANY(PC_J,SP_J,0,0);
|
||||
MAPANY(PC_K,SP_K,0,0);
|
||||
MAPANY(PC_L,SP_L,0,0);
|
||||
MAPANY(PC_Z,SP_Z,0,0);
|
||||
MAPANY(PC_X,SP_X,0,0);
|
||||
MAPANY(PC_C,SP_C,0,0);
|
||||
MAPANY(PC_V,SP_V,0,0);
|
||||
MAPANY(PC_B,SP_B,0,0);
|
||||
MAPANY(PC_N,SP_N,0,0);
|
||||
MAPANY(PC_M,SP_M,0,0);
|
||||
|
||||
MAPANY(PC_SPACE,SP_SPACE,0,0);
|
||||
MAPANY(PC_ENTER,SP_ENTER,0,0);
|
||||
MAPANY(PC_ESC,SP_BREAK,0,0);
|
||||
MAPANY(PC_CPSLOCK,SP_CPSLOCK,0,0);
|
||||
MAPANY(PC_TAB,SP_EXTEND,0,0);
|
||||
MAP(PC_BKSPACE,SP_DELETE,0,0);
|
||||
MAPANY(PC_UP,SP_UP,0,0);
|
||||
MAPANY(PC_DOWN,SP_DOWN,0,0);
|
||||
MAPANY(PC_LEFT,SP_LEFT,0,0);
|
||||
MAPANY(PC_RIGHT,SP_RIGHT,0,0);
|
||||
MAPANY(PC_F2,SP_EDIT,0,0);
|
||||
MAPANY(PC_F3,SP_TRUE,0,0);
|
||||
MAPANY(PC_F4,SP_INVERSE,0,0);
|
||||
MAP(PC_F5|MD2|MD3,0,NMI,0); // Ctrl-Alt-F5 for NMI
|
||||
MAPANY(PC_F10,SP_GRAPH,0,0); // F10 habilita el modo gráfico. Esto es para Antonio, para la BIOS
|
||||
MAP(PC_DELETE|MD2|MD3,0,URESET,0); //
|
||||
MAP(PC_KP_DOT|MD2|MD3,0,URESET,0); // Ctrl-Alt-Del for user reset
|
||||
MAP(PC_BKSPACE|MD2|MD3,0,MRESET,0); // Ctrl-Alt-BkSpace for master reset
|
||||
|
||||
//keypad
|
||||
MAPANY(PC_KP_1,SP_1,0,0);
|
||||
MAPANY(PC_KP_2,SP_2,0,0);
|
||||
MAPANY(PC_KP_3,SP_3,0,0);
|
||||
MAPANY(PC_KP_4,SP_4,0,0);
|
||||
MAPANY(PC_KP_5,SP_5,0,0);
|
||||
MAPANY(PC_KP_6,SP_6,0,0);
|
||||
MAPANY(PC_KP_7,SP_7,0,0);
|
||||
MAPANY(PC_KP_8,SP_8,0,0);
|
||||
MAPANY(PC_KP_9,SP_9,0,0);
|
||||
MAPANY(PC_KP_0,SP_0,0,0);
|
||||
MAPANY(PC_KP_DIVIS,SP_SLASH,0,0);
|
||||
MAPANY(PC_KP_MULT,SP_STAR,0,0);
|
||||
MAPANY(PC_KP_MINUS,SP_MINUS,0,0);
|
||||
MAPANY(PC_KP_PLUS,SP_PLUS,0,0);
|
||||
MAPANY(PC_KP_ENTER,SP_ENTER,0,0);
|
||||
MAPANY(PC_KP_DOT,SP_DOT,0,0);
|
||||
|
||||
MAPANY(PC_BACKSLA,SP_COLON,0,0);
|
||||
MAPANY(PC_APOSTRO,SP_DOLLAR,0,0);
|
||||
MAPANY(PC_OPNBANG,SP_EQUAL,0,0);
|
||||
MAPANY(PC_GRAVEAC,SP_PAROPEN,0,0);
|
||||
MAPANY(PC_PLUS,SP_PARCLOS,0,0);
|
||||
MAPANY(PC_EGNE,SP_SEMICOL,0,0);
|
||||
MAPANY(PC_ACUTEAC,SP_QUOTE,0,0);
|
||||
MAPANY(PC_COMMA,SP_COMMA,0,0);
|
||||
MAPANY(PC_DOT,SP_DOT,0,0);
|
||||
MAPANY(PC_MINUS,SP_SLASH,0,0);
|
||||
|
||||
MAPANY(PC_HOME,0,JOYUP,0);
|
||||
MAPANY(PC_END,0,JOYDOWN,0);
|
||||
MAPANY(PC_DELETE,0,JOYLEFT,0);
|
||||
MAPANY(PC_PGDOWN,0,JOYRIGHT,0);
|
||||
|
||||
// MAP(PC_F12,0,0,USER1); // Evento de usuario 1
|
||||
|
||||
// End of mapping. Save .HEX file for Verilog
|
||||
SAVEMAPHEX("keyb_av_hex.txt");
|
||||
// And map file for loading from ESXDOS
|
||||
SAVEMAPBIN("keymaps\\AV");
|
||||
}
|
||||
|
|
@ -333,7 +333,8 @@ int main()
|
|||
MAPANY(PC_RALT,0,JOYFIRE,MODIFIER3); // MD3 is ALT. Also is FIRE for keyboard joystick
|
||||
|
||||
MAPANY(PC_LWIN,SP_CAPS,0,0); // CAPS SHIFT
|
||||
MAPANY(PC_RWIN,SP_SYMBOL,0,0); // SYMBOL SHIFT
|
||||
MAPANY(PC_RWIN,SP_SYMBOL,0,0); // SYMBOL SHIFT
|
||||
MAPANY(PC_APPS,SP_SYMBOL,0,0); // SYMBOL SHIFT
|
||||
|
||||
// Basic mapping: each key from PC is mapped to a key in the Spectrum
|
||||
MAP(PC_1,SP_1,0,0);
|
||||
|
|
@ -482,6 +483,7 @@ int main()
|
|||
MAP(MD3|MD2|MD1|PC_LESS,SP_NOTEQ,0,0);
|
||||
|
||||
MAP(PC_F12,0,0,USER1); // Evento de usuario 1
|
||||
MAP(PC_F2|MD2,0,0,USER2); // Evento de usuario 2 = Core 2 (Ctrl+F2)
|
||||
|
||||
// End of mapping. Save .HEX file for Verilog
|
||||
SAVEMAPHEX("keyb_es_hex.txt");
|
||||
|
|
|
|||
|
|
@ -472,6 +472,9 @@ int main()
|
|||
MAP(PC_SLASH,SP_SLASH,0,0);
|
||||
MAP(MD1|PC_SLASH,SP_QUEST,0,0);
|
||||
|
||||
MAP(PC_F12,0,0,USER1); // Evento de usuario 1
|
||||
MAP(PC_F2|MD2,0,0,USER2); // Evento de usuario 2 = Core 2 (Ctrl+F2)
|
||||
|
||||
// End of mapping. Save .HEX file for Verilog
|
||||
//SAVEMAPHEX("keyb_us_hex.txt");
|
||||
// And map file for loading from ESXDOS
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1211,7 +1211,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -3259,7 +3259,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -4118,11 +4118,11 @@ C1
|
|||
00
|
||||
00
|
||||
00
|
||||
01
|
||||
61
|
||||
00
|
||||
00
|
||||
00
|
||||
02
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -5307,7 +5307,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -7355,7 +7355,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -9403,7 +9403,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -11451,7 +11451,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -13499,7 +13499,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
@ -15547,7 +15547,7 @@ E2
|
|||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
E2
|
||||
00
|
||||
00
|
||||
00
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -44,7 +44,7 @@ module memory (
|
|||
input wire [13:0] vramaddr,
|
||||
output wire [7:0] vramdout,
|
||||
output wire issue2_keyboard_enabled,
|
||||
output wire timming_ula,
|
||||
output reg [1:0] timing_mode,
|
||||
output wire disable_contention,
|
||||
output reg access_to_screen,
|
||||
|
||||
|
|
@ -68,20 +68,19 @@ module memory (
|
|||
reg divmmc_is_enabled = 1'b0;
|
||||
reg divmmc_nmi_is_disabled = 1'b0;
|
||||
reg issue2_keyboard = 1'b0;
|
||||
reg timming = 1'b0;
|
||||
initial timing_mode = 2'b00;
|
||||
reg disable_cont = 1'b0;
|
||||
reg masterconf_frozen = 1'b0;
|
||||
reg [1:0] negedge_configrom = 2'b00;
|
||||
|
||||
assign issue2_keyboard_enabled = issue2_keyboard;
|
||||
assign in_boot_mode = ~masterconf_frozen;
|
||||
assign timming_ula = timming;
|
||||
assign disable_contention = disable_cont;
|
||||
|
||||
always @(posedge clk) begin
|
||||
negedge_configrom <= {negedge_configrom[0], page_configrom_active};
|
||||
if (!mrst_n) begin
|
||||
{disable_cont,timming,issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= 6'b000001;
|
||||
{timing_mode[1],disable_cont,timing_mode[0],issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= 7'b0000001;
|
||||
masterconf_frozen <= 1'b0;
|
||||
end
|
||||
else if (page_configrom_active == 1'b1) begin
|
||||
|
|
@ -93,7 +92,7 @@ module memory (
|
|||
initial_boot_mode <= 1'b0;
|
||||
end
|
||||
else if (addr==MASTERCONF && iow) begin
|
||||
{disable_cont,timming,issue2_keyboard} <= din[5:3];
|
||||
{timing_mode[1],disable_cont,timing_mode[0],issue2_keyboard} <= din[6:3];
|
||||
if (!masterconf_frozen) begin
|
||||
masterconf_frozen <= din[7];
|
||||
{divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= din[2:0];
|
||||
|
|
@ -349,7 +348,7 @@ module memory (
|
|||
oe_n = 1'b0;
|
||||
end
|
||||
else if (addr==MASTERCONF && ior) begin
|
||||
dout = {masterconf_frozen,1'b0,disable_cont,timming,issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode};
|
||||
dout = {masterconf_frozen,timing_mode[1],disable_cont,timing_mode[0],issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode};
|
||||
oe_n = 1'b0;
|
||||
end
|
||||
else if (addr==MASTERMAPPER && ior) begin
|
||||
|
|
|
|||
|
|
@ -0,0 +1,359 @@
|
|||
module multiboot (
|
||||
input wire clk,
|
||||
input wire clk_icap, // WARNING: this clock must not be greater than 20MHz (50ns period)
|
||||
input wire rst_n,
|
||||
input wire kb_boot_core,
|
||||
input wire [7:0] zxuno_addr,
|
||||
input wire zxuno_regwr,
|
||||
input wire [7:0] din
|
||||
);
|
||||
|
||||
parameter ADDR_COREADDR = 8'hFC,
|
||||
ADDR_COREBOOT = 8'hFD;
|
||||
|
||||
reg [23:0] spi_addr = 24'h0AC000; // default: SPI address of second core as defined by the SPI memory map
|
||||
reg writting_to_spi_addr = 1'b0;
|
||||
reg writting_to_bootcore = 1'b0;
|
||||
reg boot_core = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst_n == 1'b0) begin
|
||||
writting_to_spi_addr <= 1'b0;
|
||||
writting_to_bootcore <= 1'b0;
|
||||
boot_core <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (zxuno_addr == ADDR_COREADDR) begin
|
||||
if (zxuno_regwr == 1'b1 && writting_to_spi_addr == 1'b0) begin
|
||||
spi_addr <= {spi_addr[15:0], din};
|
||||
writting_to_spi_addr <= 1'b1;
|
||||
end
|
||||
if (zxuno_regwr == 1'b0) begin
|
||||
writting_to_spi_addr <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
writting_to_spi_addr <= 1'b0;
|
||||
end
|
||||
|
||||
if (zxuno_addr == ADDR_COREBOOT) begin
|
||||
if (zxuno_regwr == 1'b1 && din[0] == 1'b1 && writting_to_bootcore == 1'b0) begin
|
||||
boot_core <= 1'b1;
|
||||
writting_to_bootcore <= 1'b1;
|
||||
end
|
||||
if (writting_to_bootcore == 1'b1) begin
|
||||
boot_core <= 1'b0;
|
||||
end
|
||||
if (zxuno_regwr == 1'b0) begin
|
||||
writting_to_bootcore <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
boot_core <= 1'b0;
|
||||
writting_to_bootcore <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [4:0] q = 5'b00000;
|
||||
reg reboot_ff = 1'b0;
|
||||
always @(posedge clk_icap) begin
|
||||
q[0] <= boot_core | kb_boot_core;
|
||||
q[1] <= q[0];
|
||||
q[2] <= q[1];
|
||||
q[3] <= q[2];
|
||||
q[4] <= q[3];
|
||||
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
|
||||
end
|
||||
|
||||
multiboot_spartan6 hacer_multiboot (
|
||||
.CLK(clk_icap),
|
||||
.MBT_RESET(1'b0),
|
||||
.MBT_REBOOT(reboot_ff),
|
||||
.spi_addr(spi_addr)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module multiboot_spartan6 (
|
||||
input wire CLK,
|
||||
input wire MBT_RESET,
|
||||
input wire MBT_REBOOT,
|
||||
input wire [23:0] spi_addr
|
||||
);
|
||||
|
||||
reg [15:0] icap_din;
|
||||
reg icap_ce;
|
||||
reg icap_wr;
|
||||
|
||||
reg [15:0] ff_icap_din_reversed;
|
||||
reg ff_icap_ce;
|
||||
reg ff_icap_wr;
|
||||
|
||||
|
||||
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
|
||||
|
||||
.CE (ff_icap_ce), // Clock enable input
|
||||
.CLK (CLK), // Clock input
|
||||
.I (ff_icap_din_reversed), // 16-bit data input
|
||||
.WRITE (ff_icap_wr) // Write input
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------
|
||||
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
|
||||
// -------------------------------------------------
|
||||
|
||||
|
||||
parameter IDLE = 0,
|
||||
SYNC_H = 1,
|
||||
SYNC_L = 2,
|
||||
|
||||
CWD_H = 3,
|
||||
CWD_L = 4,
|
||||
|
||||
GEN1_H = 5,
|
||||
GEN1_L = 6,
|
||||
|
||||
GEN2_H = 7,
|
||||
GEN2_L = 8,
|
||||
|
||||
GEN3_H = 9,
|
||||
GEN3_L = 10,
|
||||
|
||||
GEN4_H = 11,
|
||||
GEN4_L = 12,
|
||||
|
||||
GEN5_H = 13,
|
||||
GEN5_L = 14,
|
||||
|
||||
NUL_H = 15,
|
||||
NUL_L = 16,
|
||||
|
||||
MOD_H = 17,
|
||||
MOD_L = 18,
|
||||
|
||||
HCO_H = 19,
|
||||
HCO_L = 20,
|
||||
|
||||
RBT_H = 21,
|
||||
RBT_L = 22,
|
||||
|
||||
NOOP_0 = 23,
|
||||
NOOP_1 = 24,
|
||||
NOOP_2 = 25,
|
||||
NOOP_3 = 26;
|
||||
|
||||
|
||||
reg [4:0] state;
|
||||
reg [4:0] next_state;
|
||||
|
||||
|
||||
always @*
|
||||
begin: COMB
|
||||
|
||||
case (state)
|
||||
|
||||
IDLE:
|
||||
begin
|
||||
if (MBT_REBOOT)
|
||||
begin
|
||||
next_state = SYNC_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'hAA99; // Sync word 1
|
||||
end
|
||||
else
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'hFFFF; // Null
|
||||
end
|
||||
end
|
||||
|
||||
SYNC_H:
|
||||
begin
|
||||
next_state = SYNC_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h5566; // Sync word 2
|
||||
end
|
||||
|
||||
SYNC_L:
|
||||
begin
|
||||
next_state = NUL_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
NUL_H:
|
||||
begin
|
||||
// next_state = NUL_L;
|
||||
next_state = GEN1_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
|
||||
end
|
||||
|
||||
//Q
|
||||
|
||||
GEN1_H:
|
||||
begin
|
||||
next_state = GEN1_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
|
||||
end
|
||||
|
||||
GEN1_L:
|
||||
begin
|
||||
next_state = GEN2_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
|
||||
end
|
||||
|
||||
GEN2_H:
|
||||
begin
|
||||
next_state = GEN2_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3281; // Escritura a reg GENERAL_2
|
||||
end
|
||||
|
||||
GEN2_L:
|
||||
begin
|
||||
next_state = MOD_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
|
||||
end
|
||||
|
||||
/////// Registro MODE (para carga a 4x tras reboot)
|
||||
|
||||
MOD_H:
|
||||
begin
|
||||
next_state = MOD_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3301; // Escritura a reg MODE
|
||||
end
|
||||
|
||||
MOD_L:
|
||||
begin
|
||||
next_state = NUL_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
|
||||
end
|
||||
/////
|
||||
|
||||
NUL_L:
|
||||
begin
|
||||
next_state = RBT_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
RBT_H:
|
||||
begin
|
||||
next_state = RBT_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h000E; // REBOOT Command 0x000E
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
RBT_L:
|
||||
begin
|
||||
next_state = NOOP_0;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_0:
|
||||
begin
|
||||
next_state = NOOP_1;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_1:
|
||||
begin
|
||||
next_state = NOOP_2;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_2:
|
||||
begin
|
||||
next_state = NOOP_3;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
NOOP_3:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // NULL value
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // 16'h1111"
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: SEQ
|
||||
if (MBT_RESET)
|
||||
state <= IDLE;
|
||||
else
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: ICAP_FF
|
||||
|
||||
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
|
||||
ff_icap_din_reversed[1] <= icap_din[6];
|
||||
ff_icap_din_reversed[2] <= icap_din[5];
|
||||
ff_icap_din_reversed[3] <= icap_din[4];
|
||||
ff_icap_din_reversed[4] <= icap_din[3];
|
||||
ff_icap_din_reversed[5] <= icap_din[2];
|
||||
ff_icap_din_reversed[6] <= icap_din[1];
|
||||
ff_icap_din_reversed[7] <= icap_din[0];
|
||||
ff_icap_din_reversed[8] <= icap_din[15];
|
||||
ff_icap_din_reversed[9] <= icap_din[14];
|
||||
ff_icap_din_reversed[10] <= icap_din[13];
|
||||
ff_icap_din_reversed[11] <= icap_din[12];
|
||||
ff_icap_din_reversed[12] <= icap_din[11];
|
||||
ff_icap_din_reversed[13] <= icap_din[10];
|
||||
ff_icap_din_reversed[14] <= icap_din[9];
|
||||
ff_icap_din_reversed[15] <= icap_din[8];
|
||||
|
||||
ff_icap_ce <= icap_ce;
|
||||
ff_icap_wr <= icap_wr;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,359 @@
|
|||
module multiboot (
|
||||
input wire clk,
|
||||
input wire clk_icap, // WARNING: this clock must not be greater than 20MHz (50ns period)
|
||||
input wire rst_n,
|
||||
input wire kb_boot_core,
|
||||
input wire [7:0] zxuno_addr,
|
||||
input wire zxuno_regwr,
|
||||
input wire [7:0] din
|
||||
);
|
||||
|
||||
parameter ADDR_COREADDR = 8'hFC,
|
||||
ADDR_COREBOOT = 8'hFD;
|
||||
|
||||
reg [23:0] spi_addr = 24'h0AC000; // default: SPI address of second core as defined by the SPI memory map
|
||||
reg writting_to_spi_addr = 1'b0;
|
||||
reg writting_to_bootcore = 1'b0;
|
||||
reg boot_core = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst_n == 1'b0) begin
|
||||
writting_to_spi_addr <= 1'b0;
|
||||
writting_to_bootcore <= 1'b0;
|
||||
boot_core <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (zxuno_addr == ADDR_COREADDR) begin
|
||||
if (zxuno_regwr == 1'b1 && writting_to_spi_addr == 1'b0) begin
|
||||
spi_addr <= {spi_addr[15:0], din};
|
||||
writting_to_spi_addr <= 1'b1;
|
||||
end
|
||||
if (zxuno_regwr == 1'b0) begin
|
||||
writting_to_spi_addr <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
writting_to_spi_addr <= 1'b0;
|
||||
end
|
||||
|
||||
if (zxuno_addr == ADDR_COREBOOT) begin
|
||||
if (zxuno_regwr == 1'b1 && din[0] == 1'b1 && writting_to_bootcore == 1'b0) begin
|
||||
boot_core <= 1'b1;
|
||||
writting_to_bootcore <= 1'b1;
|
||||
end
|
||||
if (writting_to_bootcore == 1'b1) begin
|
||||
boot_core <= 1'b0;
|
||||
end
|
||||
if (zxuno_regwr == 1'b0) begin
|
||||
writting_to_bootcore <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
boot_core <= 1'b0;
|
||||
writting_to_bootcore <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [4:0] q = 5'b00000;
|
||||
reg reboot_ff = 1'b0;
|
||||
always @(posedge clk_icap) begin
|
||||
q[0] <= boot_core | kb_boot_core;
|
||||
q[1] <= q[0];
|
||||
q[2] <= q[1];
|
||||
q[3] <= q[2];
|
||||
q[4] <= q[3];
|
||||
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
|
||||
end
|
||||
|
||||
multiboot_spartan6 hacer_multiboot (
|
||||
.CLK(clk_icap),
|
||||
.MBT_RESET(1'b0),
|
||||
.MBT_REBOOT(reboot_ff),
|
||||
.spi_addr(spi_addr)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module multiboot_spartan6 (
|
||||
input wire CLK,
|
||||
input wire MBT_RESET,
|
||||
input wire MBT_REBOOT,
|
||||
input wire [23:0] spi_addr
|
||||
);
|
||||
|
||||
reg [15:0] icap_din;
|
||||
reg icap_ce;
|
||||
reg icap_wr;
|
||||
|
||||
reg [15:0] ff_icap_din_reversed;
|
||||
reg ff_icap_ce;
|
||||
reg ff_icap_wr;
|
||||
|
||||
|
||||
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
|
||||
|
||||
.CE (ff_icap_ce), // Clock enable input
|
||||
.CLK (CLK), // Clock input
|
||||
.I (ff_icap_din_reversed), // 16-bit data input
|
||||
.WRITE (ff_icap_wr) // Write input
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------
|
||||
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
|
||||
// -------------------------------------------------
|
||||
|
||||
|
||||
parameter IDLE = 0,
|
||||
SYNC_H = 1,
|
||||
SYNC_L = 2,
|
||||
|
||||
CWD_H = 3,
|
||||
CWD_L = 4,
|
||||
|
||||
GEN1_H = 5,
|
||||
GEN1_L = 6,
|
||||
|
||||
GEN2_H = 7,
|
||||
GEN2_L = 8,
|
||||
|
||||
GEN3_H = 9,
|
||||
GEN3_L = 10,
|
||||
|
||||
GEN4_H = 11,
|
||||
GEN4_L = 12,
|
||||
|
||||
GEN5_H = 13,
|
||||
GEN5_L = 14,
|
||||
|
||||
NUL_H = 15,
|
||||
NUL_L = 16,
|
||||
|
||||
MOD_H = 17,
|
||||
MOD_L = 18,
|
||||
|
||||
HCO_H = 19,
|
||||
HCO_L = 20,
|
||||
|
||||
RBT_H = 21,
|
||||
RBT_L = 22,
|
||||
|
||||
NOOP_0 = 23,
|
||||
NOOP_1 = 24,
|
||||
NOOP_2 = 25,
|
||||
NOOP_3 = 26;
|
||||
|
||||
|
||||
reg [4:0] state;
|
||||
reg [4:0] next_state;
|
||||
|
||||
|
||||
always @*
|
||||
begin: COMB
|
||||
|
||||
case (state)
|
||||
|
||||
IDLE:
|
||||
begin
|
||||
if (MBT_REBOOT)
|
||||
begin
|
||||
next_state = SYNC_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'hAA99; // Sync word 1
|
||||
end
|
||||
else
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'hFFFF; // Null
|
||||
end
|
||||
end
|
||||
|
||||
SYNC_H:
|
||||
begin
|
||||
next_state = SYNC_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h5566; // Sync word 2
|
||||
end
|
||||
|
||||
SYNC_L:
|
||||
begin
|
||||
next_state = NUL_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
NUL_H:
|
||||
begin
|
||||
// next_state = NUL_L;
|
||||
next_state = GEN1_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
|
||||
end
|
||||
|
||||
//Q
|
||||
|
||||
GEN1_H:
|
||||
begin
|
||||
next_state = GEN1_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
|
||||
end
|
||||
|
||||
GEN1_L:
|
||||
begin
|
||||
next_state = GEN2_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
|
||||
end
|
||||
|
||||
GEN2_H:
|
||||
begin
|
||||
next_state = GEN2_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3281; // Escritura a reg GENERAL_2
|
||||
end
|
||||
|
||||
GEN2_L:
|
||||
begin
|
||||
next_state = MOD_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
|
||||
end
|
||||
|
||||
/////// Registro MODE (para carga a 4x tras reboot)
|
||||
|
||||
MOD_H:
|
||||
begin
|
||||
next_state = MOD_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3301; // Escritura a reg MODE
|
||||
end
|
||||
|
||||
MOD_L:
|
||||
begin
|
||||
next_state = NUL_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
|
||||
end
|
||||
/////
|
||||
|
||||
NUL_L:
|
||||
begin
|
||||
next_state = RBT_H;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h30A1; // Write to Command Register....
|
||||
end
|
||||
|
||||
RBT_H:
|
||||
begin
|
||||
next_state = RBT_L;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h000E; // REBOOT Command 0x000E
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
RBT_L:
|
||||
begin
|
||||
next_state = NOOP_0;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_0:
|
||||
begin
|
||||
next_state = NOOP_1;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_1:
|
||||
begin
|
||||
next_state = NOOP_2;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
NOOP_2:
|
||||
begin
|
||||
next_state = NOOP_3;
|
||||
icap_ce = 0;
|
||||
icap_wr = 0;
|
||||
icap_din = 16'h2000; // NOOP
|
||||
end
|
||||
|
||||
//--------------------
|
||||
|
||||
NOOP_3:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // NULL value
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
next_state = IDLE;
|
||||
icap_ce = 1;
|
||||
icap_wr = 1;
|
||||
icap_din = 16'h1111; // 16'h1111"
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: SEQ
|
||||
if (MBT_RESET)
|
||||
state <= IDLE;
|
||||
else
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge CLK)
|
||||
|
||||
begin: ICAP_FF
|
||||
|
||||
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
|
||||
ff_icap_din_reversed[1] <= icap_din[6];
|
||||
ff_icap_din_reversed[2] <= icap_din[5];
|
||||
ff_icap_din_reversed[3] <= icap_din[4];
|
||||
ff_icap_din_reversed[4] <= icap_din[3];
|
||||
ff_icap_din_reversed[5] <= icap_din[2];
|
||||
ff_icap_din_reversed[6] <= icap_din[1];
|
||||
ff_icap_din_reversed[7] <= icap_din[0];
|
||||
ff_icap_din_reversed[8] <= icap_din[15];
|
||||
ff_icap_din_reversed[9] <= icap_din[14];
|
||||
ff_icap_din_reversed[10] <= icap_din[13];
|
||||
ff_icap_din_reversed[11] <= icap_din[12];
|
||||
ff_icap_din_reversed[12] <= icap_din[11];
|
||||
ff_icap_din_reversed[13] <= icap_din[10];
|
||||
ff_icap_din_reversed[14] <= icap_din[9];
|
||||
ff_icap_din_reversed[15] <= icap_din[8];
|
||||
|
||||
ff_icap_ce <= icap_ce;
|
||||
ff_icap_wr <= icap_wr;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 18:02:15 03/12/2015
|
||||
// Design Name:
|
||||
// Module Name: pal_generator
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module pal_sync_generator (
|
||||
input wire clk,
|
||||
input wire [1:0] mode, // 00: 48K, 01: 128K, 10: Pentagon, 11: Reserved
|
||||
|
||||
input wire rasterint_enable,
|
||||
input wire vretraceint_disable,
|
||||
input wire [8:0] raster_line,
|
||||
output wire raster_int_in_progress,
|
||||
|
||||
input wire [2:0] ri,
|
||||
input wire [2:0] gi,
|
||||
input wire [2:0] bi,
|
||||
output wire [8:0] hcnt,
|
||||
output wire [8:0] vcnt,
|
||||
output reg [2:0] ro,
|
||||
output reg [2:0] go,
|
||||
output reg [2:0] bo,
|
||||
output reg hsync,
|
||||
output reg vsync,
|
||||
output wire int_n
|
||||
);
|
||||
|
||||
reg [8:0] hc = 9'h000;
|
||||
reg [8:0] vc = 9'h000;
|
||||
|
||||
reg [8:0] end_count_h = 9'd447;
|
||||
reg [8:0] end_count_v = 9'd311;
|
||||
reg [8:0] begin_hblank = 9'd320;
|
||||
reg [8:0] end_hblank = 9'd415;
|
||||
reg [8:0] begin_hsync = 9'd344;
|
||||
reg [8:0] end_hsync = 9'd375;
|
||||
reg [8:0] begin_vblank = 9'd248;
|
||||
reg [8:0] end_vblank = 9'd255;
|
||||
reg [8:0] begin_vsync = 9'd248;
|
||||
reg [8:0] end_vsync = 9'd251;
|
||||
reg [8:0] begin_vcint = 9'd248;
|
||||
reg [8:0] end_vcint = 9'd248;
|
||||
reg [8:0] begin_hcint = 9'd2;
|
||||
reg [8:0] end_hcint = 9'd65;
|
||||
|
||||
reg [1:0] old_mode = 2'b11;
|
||||
|
||||
assign hcnt = hc;
|
||||
assign vcnt = vc;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (hc == end_count_h) begin
|
||||
hc <= 0;
|
||||
if (vc == end_count_v) begin
|
||||
vc <= 0;
|
||||
if (mode != old_mode) begin
|
||||
old_mode <= mode;
|
||||
case (mode)
|
||||
2'b00: begin // timings for Sinclair 48K
|
||||
end_count_h <= 9'd447;
|
||||
end_count_v <= 9'd311;
|
||||
begin_hblank <= 9'd320;
|
||||
end_hblank <= 9'd415;
|
||||
begin_hsync <= 9'd344;
|
||||
end_hsync <= 9'd375;
|
||||
begin_vblank <= 9'd248;
|
||||
end_vblank <= 9'd255;
|
||||
begin_vsync <= 9'd248;
|
||||
end_vsync <= 9'd251;
|
||||
begin_vcint <= 9'd248;
|
||||
end_vcint <= 9'd248;
|
||||
begin_hcint <= 9'd2;
|
||||
end_hcint <= 9'd65;
|
||||
end
|
||||
2'b01: begin // timings for Sinclair 128K/+2 grey
|
||||
end_count_h <= 9'd455;
|
||||
end_count_v <= 9'd310;
|
||||
begin_hblank <= 9'd320;
|
||||
end_hblank <= 9'd415;
|
||||
begin_hsync <= 9'd344;
|
||||
end_hsync <= 9'd375;
|
||||
begin_vblank <= 9'd248;
|
||||
end_vblank <= 9'd255;
|
||||
begin_vsync <= 9'd248;
|
||||
end_vsync <= 9'd251;
|
||||
begin_vcint <= 9'd248;
|
||||
end_vcint <= 9'd248;
|
||||
begin_hcint <= 9'd2;
|
||||
end_hcint <= 9'd65;
|
||||
end
|
||||
2'b10,
|
||||
2'b11: begin // timings for Pentagon 128
|
||||
end_count_h <= 9'd447;
|
||||
end_count_v <= 9'd319;
|
||||
begin_hblank <= 9'd336; // 9'd328;
|
||||
end_hblank <= 9'd399; // 9'd391;
|
||||
begin_hsync <= 9'd336; // 9'd328;
|
||||
end_hsync <= 9'd367; // 9'd359;
|
||||
begin_vblank <= 9'd240;
|
||||
end_vblank <= 9'd271; // 9'd255;
|
||||
begin_vsync <= 9'd240;
|
||||
end_vsync <= 9'd255; // 9'd243;
|
||||
begin_vcint <= 9'd239;
|
||||
end_vcint <= 9'd239;
|
||||
begin_hcint <= 9'd320; // 9'd318;
|
||||
end_hcint <= 9'd391; //9'd389;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else
|
||||
vc <= vc + 1;
|
||||
end
|
||||
else
|
||||
hc <= hc + 1;
|
||||
end
|
||||
|
||||
// INT generation
|
||||
reg vretrace_int_n, raster_int_n;
|
||||
assign int_n = vretrace_int_n & raster_int_n;
|
||||
assign raster_int_in_progress = ~raster_int_n;
|
||||
always @* begin
|
||||
vretrace_int_n = 1'b1;
|
||||
if (vretraceint_disable == 1'b0 && (hc >= begin_hcint && vc == begin_vcint) && (hc <= end_hcint && vc == end_vcint))
|
||||
vretrace_int_n = 1'b0;
|
||||
|
||||
raster_int_n = 1'b1;
|
||||
if (rasterint_enable == 1'b1 && hc >= 256 && hc <= 319) begin
|
||||
if (raster_line == 9'd0 && vc == end_count_v)
|
||||
raster_int_n = 1'b0;
|
||||
if (raster_line != 9'd0 && vc == (raster_line - 9'd1))
|
||||
raster_int_n = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
ro = ri;
|
||||
go = gi;
|
||||
bo = bi;
|
||||
hsync = 1'b1;
|
||||
vsync = 1'b1;
|
||||
if ( (hc >= begin_hblank && hc <= end_hblank) || (vc >= begin_vblank && vc <= end_vblank) ) begin
|
||||
ro = 3'b000;
|
||||
go = 3'b000;
|
||||
bo = 3'b000;
|
||||
if (hc >= begin_hsync && hc <= end_hsync)
|
||||
hsync = 1'b0;
|
||||
if (vc >= begin_vsync && vc <= end_vsync)
|
||||
vsync = 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,31 +1,32 @@
|
|||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="ParStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>3241</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>13509</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>13509</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>12464</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.9 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>17.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>19.5 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>49.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>64.7 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>64.7 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>64.7 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>65.7 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>67.0 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.6</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>4226</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>16414</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>16414</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>15400</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>17.3 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>20.2 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>43.7 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>45.4 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>69.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>69.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>69.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>69.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>70.8 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>73.1 sec</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>2.5</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.9</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>8.8</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>10.5109</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
|
||||
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>8.5515</xtag-par-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
</TABLE>
|
||||
|
|
|
|||
|
|
@ -1,84 +1,85 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
NET "sysclk" PERIOD=35 ns;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33; #87
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
NET "sysclk" PERIOD=35 ns;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
NET "sysclk" PERIOD=35 ns;
|
||||
|
||||
# Video output
|
||||
NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
NET "sram_addr<0>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<1>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<2>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<3>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<4>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<5>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<7>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<8>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<9>" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<10>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<11>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<12>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<13>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<14>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<16>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<17>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<18>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_we_n" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
#NET "btn2" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5
|
||||
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
NET "sysclk" PERIOD=35 ns;
|
||||
|
||||
# Video output
|
||||
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33; #87
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,641 @@
|
|||
//*****************************************************************************
|
||||
// Company: Xilinx
|
||||
// Engineer: Karl Kurbjun and Carl Ribbing
|
||||
// Design Name: PLL DRP
|
||||
// Module Name: pll_drp_func.h
|
||||
// Project Name:
|
||||
// Target Devices: Virtex 5 and Spartan 6 Family
|
||||
// Tool versions: L.50 (lin)
|
||||
// Description: This header provides the functions necessary to calculate
|
||||
// the DRP register values for the V5 PLL
|
||||
//*****************************************************************************
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers.
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
$display("ERROR: duty_cycle: %f is invalid", duty_cycle);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates delay_time and phase_mux based on the divide and
|
||||
// phase
|
||||
function [16:0] pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
pll_phase={phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] v5_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
v5_pll_lock_lookup = lookup[ ((divide-1)*40) +: 40];
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [39:0] s6_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b01001_00111_1111101000_1111101001_0000000001,//1
|
||||
40'b01001_00111_1111101000_1111101001_0000000001,//2
|
||||
40'b01101_01011_1111101000_1111101001_0000000001,//3
|
||||
40'b10010_10000_1111101000_1111101001_0000000001,//4
|
||||
40'b10110_10100_1111101000_1111101001_0000000001,//5
|
||||
40'b11010_11000_1111101000_1111101001_0000000001,//6
|
||||
40'b11111_11101_1111101000_1111101001_0000000001,//7
|
||||
40'b11111_11101_1111101000_1111101001_0000000001,//8
|
||||
40'b11111_11101_1111101000_1111101001_0000000001,//9
|
||||
40'b11111_11101_1111101000_1111101001_0000000001,//10
|
||||
40'b11111_11101_1110000100_1111101001_0000000001,//11
|
||||
40'b11111_11101_1100111001_1111101001_0000000001,//12
|
||||
40'b11111_11101_1011101110_1111101001_0000000001,//13
|
||||
40'b11111_11101_1010111100_1111101001_0000000001,//14
|
||||
40'b11111_11101_1010001010_1111101001_0000000001,//15
|
||||
40'b11111_11101_1001110001_1111101001_0000000001,//16
|
||||
40'b11111_11101_1000111111_1111101001_0000000001,//17
|
||||
40'b11111_11101_1000100110_1111101001_0000000001,//18
|
||||
40'b11111_11101_1000001101_1111101001_0000000001,//19
|
||||
40'b11111_11101_0111110100_1111101001_0000000001,//20
|
||||
40'b11111_11101_0111011011_1111101001_0000000001,//21
|
||||
40'b11111_11101_0111000010_1111101001_0000000001,//22
|
||||
40'b11111_11101_0110101001_1111101001_0000000001,//23
|
||||
40'b11111_11101_0110010000_1111101001_0000000001,//24
|
||||
40'b11111_11101_0110010000_1111101001_0000000001,//25
|
||||
40'b11111_11101_0101110111_1111101001_0000000001,//26
|
||||
40'b11111_11101_0101011110_1111101001_0000000001,//27
|
||||
40'b11111_11101_0101011110_1111101001_0000000001,//28
|
||||
40'b11111_11101_0101000101_1111101001_0000000001,//29
|
||||
40'b11111_11101_0101000101_1111101001_0000000001,//30
|
||||
40'b11111_11101_0100101100_1111101001_0000000001,//31
|
||||
40'b11111_11101_0100101100_1111101001_0000000001,//32
|
||||
40'b11111_11101_0100101100_1111101001_0000000001,//33
|
||||
40'b11111_11101_0100010011_1111101001_0000000001,//34
|
||||
40'b11111_11101_0100010011_1111101001_0000000001,//35
|
||||
40'b11111_11101_0100010011_1111101001_0000000001,//36
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//37
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//38
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//39
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//40
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//41
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//42
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//43
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//44
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//45
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//46
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//47
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//48
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//49
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//50
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//51
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//52
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//53
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//54
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//55
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//56
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//57
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//58
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//59
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//60
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//61
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//62
|
||||
40'b11111_11101_0011111010_1111101001_0000000001,//63
|
||||
40'b11111_11101_0011111010_1111101001_0000000001//64
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
s6_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
|
||||
$display("lock_lookup: %b", s6_pll_lock_lookup);
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] v5_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [1279:0] lookup;
|
||||
|
||||
reg [19:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed as:
|
||||
// High bndwidth__Low bndwidth
|
||||
// RES_LFHF_CP__RES_LFHF_CP
|
||||
20'b1111_00_0101__0001_11_0111, // 1
|
||||
20'b1111_00_1111__0001_11_0101, // 2
|
||||
20'b1101_00_1111__0001_11_1110, // 3
|
||||
20'b1001_00_1111__0001_11_0110, // 4
|
||||
20'b1110_00_1111__0001_11_1010, // 5
|
||||
20'b0001_00_1111__0001_11_1100, // 6
|
||||
20'b0001_00_1111__0001_11_1100, // 7
|
||||
20'b0110_00_1111__0001_11_1100, // 8
|
||||
20'b1010_00_1111__0001_11_1100, // 9
|
||||
20'b1010_00_1111__0001_11_0010, // 10
|
||||
20'b1010_00_1111__0001_11_0010, // 11
|
||||
20'b1100_00_1110__0001_11_0010, // 12
|
||||
20'b1100_00_1111__0001_11_1100, // 13
|
||||
20'b1100_00_1111__0001_11_0100, // 14
|
||||
20'b1100_00_1111__0001_11_0100, // 15
|
||||
20'b1100_00_1111__0001_11_0100, // 16
|
||||
20'b1100_00_1111__0001_11_0100, // 17
|
||||
20'b1100_00_1111__0001_11_0100, // 18
|
||||
20'b1100_00_1111__0001_11_0100, // 19
|
||||
20'b1100_00_1111__0001_11_0100, // 20
|
||||
20'b1100_00_1110__0001_11_0100, // 21
|
||||
20'b1100_00_1110__0001_11_0100, // 22
|
||||
20'b1100_00_1110__0001_11_0100, // 23
|
||||
20'b1010_00_1111__0001_11_1000, // 24
|
||||
20'b1100_00_1101__0001_11_1000, // 25
|
||||
20'b0010_00_1100__0001_11_1000, // 26
|
||||
20'b1100_00_1101__0001_11_1000, // 27
|
||||
20'b1100_00_1101__0001_11_1000, // 28
|
||||
20'b1010_00_1111__0001_11_1000, // 29
|
||||
20'b1010_00_1111__0001_11_1000, // 30
|
||||
20'b1010_00_1111__0001_11_1000, // 31
|
||||
20'b0010_00_0111__0001_11_1000, // 32
|
||||
20'b1100_00_1100__0001_11_1000, // 33
|
||||
20'b1100_00_1100__0001_11_1000, // 34
|
||||
20'b1010_00_1110__0001_11_1000, // 35
|
||||
20'b0010_00_0110__0001_11_1000, // 36
|
||||
20'b0010_00_0110__0001_11_1000, // 37
|
||||
20'b0010_00_0110__0010_11_0100, // 38
|
||||
20'b1100_00_0111__0010_11_0100, // 39
|
||||
20'b0010_00_0110__0010_11_0100, // 40
|
||||
20'b0100_00_0100__0010_11_0100, // 41
|
||||
20'b0100_00_0100__0010_11_0100, // 42
|
||||
20'b0100_00_0100__0010_11_0100, // 43
|
||||
20'b0100_00_0100__0010_11_0100, // 44
|
||||
20'b0100_00_0100__0010_11_0100, // 45
|
||||
20'b0100_00_0100__0010_11_0100, // 46
|
||||
20'b1000_00_0011__0010_11_0100, // 47
|
||||
20'b1000_00_0011__0010_11_1000, // 48
|
||||
20'b1000_00_0011__0010_11_1000, // 49
|
||||
20'b1000_00_0011__0010_11_1000, // 50
|
||||
20'b1000_00_0011__0010_11_1000, // 51
|
||||
20'b1000_00_0011__0010_11_1000, // 52
|
||||
20'b1000_00_0011__0010_11_1000, // 53
|
||||
20'b1000_00_0011__0010_11_1000, // 54
|
||||
20'b1000_00_0011__0010_11_1000, // 55
|
||||
20'b1000_00_0011__0010_11_1000, // 56
|
||||
20'b1000_00_0011__0010_11_1000, // 57
|
||||
20'b1000_00_0011__0010_11_1000, // 58
|
||||
20'b1000_00_0011__0010_11_1000, // 59
|
||||
20'b1000_00_0011__0010_11_1000, // 60
|
||||
20'b1000_00_0011__0010_11_1000, // 61
|
||||
20'b1000_00_0011__0010_11_1000, // 62
|
||||
20'b1000_00_0011__0010_11_1000, // 63
|
||||
20'b1000_00_0011__0010_11_1000 // 64
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
lookup_entry = lookup[ ((divide-1)*20) +: 20];
|
||||
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
v5_pll_filter_lookup=lookup_entry[9:0];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
v5_pll_filter_lookup=lookup_entry[19:10];
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [9:0] s6_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [1279:0] lookup;
|
||||
|
||||
reg [19:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed as:
|
||||
// High bndwidth__Low bndwidth
|
||||
// RES_LFHF_CP__RES_LFHF_CP
|
||||
20'b1011_11_0010__1101_11_0001,//1
|
||||
20'b1111_11_0101__1110_11_0001,//2
|
||||
20'b1011_11_0110__0001_11_0001,//3
|
||||
20'b1111_11_1110__0110_11_0001,//4
|
||||
20'b1011_11_1110__1010_11_0001,//5
|
||||
20'b1101_11_1110__1100_11_0001,//6
|
||||
20'b0011_11_1111__1100_11_0001,//7
|
||||
20'b0101_11_1111__1100_11_0001,//8
|
||||
20'b1001_11_1111__0010_11_0001,//9
|
||||
20'b1110_11_1110__0010_11_0001,//10
|
||||
20'b1110_11_1111__0100_11_0001,//11
|
||||
20'b0001_11_1111__0100_11_0001,//12
|
||||
20'b0001_11_1111__0100_11_0001,//13
|
||||
20'b0110_11_1110__0100_11_0001,//14
|
||||
20'b0110_11_1110__0100_11_0001,//15
|
||||
20'b1010_11_1110__0100_11_0001,//16
|
||||
20'b1010_11_1110__0100_11_0001,//17
|
||||
20'b1010_11_1111__0100_11_0001,//18
|
||||
20'b1010_11_1111__0100_11_0001,//19
|
||||
20'b1010_11_1111__0100_11_0001,//20
|
||||
20'b1010_11_1111__0100_11_0001,//21
|
||||
20'b1100_11_1101__1000_11_0001,//22
|
||||
20'b1100_11_1101__1000_11_0001,//23
|
||||
20'b1100_11_1110__1000_11_0001,//24
|
||||
20'b1100_11_1110__1000_11_0001,//25
|
||||
20'b1100_11_1111__1000_11_0001,//26
|
||||
20'b1100_11_1111__1000_11_0001,//27
|
||||
20'b1100_11_1111__1000_11_0001,//28
|
||||
20'b1100_11_1111__1000_11_0001,//29
|
||||
20'b1100_11_1111__1000_11_0001,//30
|
||||
20'b0010_11_1110__1000_11_0001,//31
|
||||
20'b0010_11_1110__1000_11_0001,//32
|
||||
20'b1100_11_1111__1000_11_0001,//33
|
||||
20'b1100_11_1111__1000_11_0001,//34
|
||||
20'b0010_11_1101__0100_11_0010,//35
|
||||
20'b0010_11_1101__0100_11_0010,//36
|
||||
20'b0100_11_1111__0100_11_0010,//37
|
||||
20'b0010_11_1100__0100_11_0010,//38
|
||||
20'b0010_11_1100__0100_11_0010,//39
|
||||
20'b0010_11_1100__0100_11_0010,//40
|
||||
20'b1000_11_0100__0100_11_0010,//41
|
||||
20'b1000_11_0100__0100_11_0010,//42
|
||||
20'b1000_11_0100__0100_11_0010,//43
|
||||
20'b0100_11_0101__1000_11_0010,//44
|
||||
20'b0010_11_0111__1000_11_0010,//45
|
||||
20'b1000_11_0011__1000_11_0010,//46
|
||||
20'b1000_11_0011__1000_11_0010,//47
|
||||
20'b1000_11_0011__1000_11_0010,//48
|
||||
20'b1000_11_0011__1000_11_0010,//49
|
||||
20'b1000_11_0011__1000_11_0010,//50
|
||||
20'b1000_11_0011__1000_11_0010,//51
|
||||
20'b1000_11_0011__1000_11_0010,//52
|
||||
20'b1000_11_0011__1000_11_0010,//53
|
||||
20'b1000_11_0011__1000_11_0010,//54
|
||||
20'b1000_11_0011__1000_11_0010,//55
|
||||
20'b1000_11_0011__1000_11_0010,//56
|
||||
20'b0100_11_0011__1000_11_0010,//57
|
||||
20'b0100_11_0011__1000_11_0010,//58
|
||||
20'b0100_11_0011__1000_11_0010,//59
|
||||
20'b0100_11_0011__1000_11_0010,//60
|
||||
20'b0100_11_0011__1000_11_0010,//61
|
||||
20'b0100_11_0011__1000_11_0010,//62
|
||||
20'b0100_11_0011__1000_11_0010,//63
|
||||
20'b0100_11_0011__1000_11_0010//64
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
lookup_entry = lookup[ ((64-divide)*20) +: 20];
|
||||
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
s6_pll_filter_lookup=lookup_entry[9:0];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
s6_pll_filter_lookup=lookup_entry[19:10];
|
||||
end
|
||||
|
||||
$display("filter_lookup: %b", s6_pll_filter_lookup);
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle settings to
|
||||
// calculate the upper and lower counter registers.
|
||||
function [37:0] v5_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = pll_divider(divide, duty_cycle);
|
||||
// pm[8:6], dt[5:0]
|
||||
phase_calc = pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12], phase_calc[5:0], phase_calc[8:6]);
|
||||
`endif
|
||||
|
||||
v5_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
8'h00, div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [22:0] s6_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [8:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = pll_divider(divide, duty_cycle);
|
||||
// pm[8:6], dt[5:0]
|
||||
phase_calc = pll_phase(divide, phase);
|
||||
|
||||
// Return value is
|
||||
// PHASE_MUX [22:20]
|
||||
// DELAY_TIME [19:14]
|
||||
// EDGE [13]
|
||||
// NOCOUNT [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12], phase_calc[5:0], phase_calc[8:6]);
|
||||
`endif
|
||||
|
||||
s6_pll_count_calc =
|
||||
{
|
||||
phase_calc[8:0],
|
||||
div_calc[13:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Karl Kurbjun and Carl Ribbing
|
||||
// Date: 2/19/2009
|
||||
// Design Name: PLL DRP
|
||||
// Module Name: top.v
|
||||
// Version: 1.0
|
||||
// Target Devices: Spartan 6 Family
|
||||
// Tool versions: L.68 (lin)
|
||||
// Description: This is a basic demonstration of the PLL_DRP
|
||||
// connectivity to the PLL_ADV.
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2008 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module pll_top
|
||||
(
|
||||
// SSTEP is the input to start a reconfiguration. It should only be
|
||||
// pulsed for one clock cycle.
|
||||
input wire SSTEP,
|
||||
// STATE determines which state the PLL_ADV will be reconfigured to. A
|
||||
// value of 0 correlates to state 1, and a value of 1 correlates to state
|
||||
// 2.
|
||||
input wire [2:0] STATE,
|
||||
|
||||
// RST will reset the entire reference design including the PLL_ADV
|
||||
input wire RST,
|
||||
// CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the
|
||||
// clock for the PLL_DRP module
|
||||
input wire CLKIN,
|
||||
|
||||
// SRDY pulses for one clock cycle after the PLL_ADV is locked and the
|
||||
// PLL_DRP module is ready to start another re-configuration
|
||||
output wire SRDY,
|
||||
|
||||
// These are the clock outputs from the PLL_ADV.
|
||||
output wire CLK0OUT,
|
||||
output wire CLK1OUT,
|
||||
output wire CLK2OUT,
|
||||
output wire CLK3OUT,
|
||||
output wire CLK4OUT,
|
||||
output wire CLK5OUT
|
||||
);
|
||||
|
||||
// These signals are used as direct connections between the PLL_ADV and the
|
||||
// PLL_DRP.
|
||||
wire [15:0] di;
|
||||
wire [4:0] daddr;
|
||||
wire [15:0] dout;
|
||||
wire den;
|
||||
wire dwe;
|
||||
wire dclk;
|
||||
wire rst_pll;
|
||||
wire drdy;
|
||||
wire locked;
|
||||
|
||||
// These signals are used for the BUFG's necessary for the design.
|
||||
wire clkin_bufgout;
|
||||
|
||||
wire clkfb_bufgout;
|
||||
wire clkfb_bufgin;
|
||||
|
||||
wire clk0_bufgin;
|
||||
wire clk0_bufgout;
|
||||
|
||||
wire clk1_bufgin;
|
||||
wire clk1_bufgout;
|
||||
|
||||
wire clk2_bufgin;
|
||||
wire clk2_bufgout;
|
||||
|
||||
wire clk3_bufgin;
|
||||
wire clk3_bufgout;
|
||||
|
||||
wire clk4_bufgin;
|
||||
wire clk4_bufgout;
|
||||
|
||||
wire clk5_bufgin;
|
||||
wire clk5_bufgout;
|
||||
|
||||
// Global buffers used in design
|
||||
// BUFG BUFG_IN (
|
||||
// .O(clkin_bufgout),
|
||||
// .I(CLKIN)
|
||||
// );
|
||||
assign clkin_bufgout = CLKIN;
|
||||
|
||||
BUFG BUFG_FB (
|
||||
.O(clkfb_bufgout),
|
||||
.I(clkfb_bufgin)
|
||||
);
|
||||
|
||||
BUFG BUFG_CLK0 (
|
||||
.O(CLK0OUT),
|
||||
.I(clk0_bufgin)
|
||||
);
|
||||
|
||||
BUFG BUFG_CLK1 (
|
||||
.O(CLK1OUT),
|
||||
.I(clk1_bufgin)
|
||||
);
|
||||
|
||||
BUFG BUFG_CLK2 (
|
||||
.O(CLK2OUT),
|
||||
.I(clk2_bufgin)
|
||||
);
|
||||
|
||||
BUFG BUFG_CLK3 (
|
||||
.O(CLK3OUT),
|
||||
.I(clk3_bufgin)
|
||||
);
|
||||
|
||||
BUFG BUFG_CLK4 (
|
||||
.O(CLK4OUT),
|
||||
.I(clk4_bufgin)
|
||||
);
|
||||
|
||||
BUFG BUFG_CLK5 (
|
||||
.O(CLK5OUT),
|
||||
.I(clk5_bufgin)
|
||||
);
|
||||
|
||||
// // ODDR registers used to output clocks
|
||||
//
|
||||
// ODDR2 #(
|
||||
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
|
||||
// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
||||
// ) ODDR2_CLK0 (
|
||||
// .Q(CLK0OUT), // 1-bit DDR output data
|
||||
// .C0(clk0_bufgout), // 1-bit clock input
|
||||
// .C1(~clk0_bufgout), // 1-bit clock input
|
||||
// .CE(1'b1), // 1-bit clock enable input
|
||||
// .D0(1'b1), // 1-bit data input (associated with C0)
|
||||
// .D1(1'b0), // 1-bit data input (associated with C1)
|
||||
// .R(RST), // 1-bit reset input
|
||||
// .S(1'b0) // 1-bit set input
|
||||
// );
|
||||
//
|
||||
// ODDR2 #(
|
||||
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
|
||||
// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
||||
// ) ODDR2_CLK1 (
|
||||
// .Q(CLK1OUT), // 1-bit DDR output data
|
||||
// .C0(clk1_bufgout), // 1-bit clock input
|
||||
// .C1(~clk1_bufgout), // 1-bit clock input
|
||||
// .CE(1'b1), // 1-bit clock enable input
|
||||
// .D0(1'b1), // 1-bit data input (associated with C0)
|
||||
// .D1(1'b0), // 1-bit data input (associated with C1)
|
||||
// .R(RST), // 1-bit reset input
|
||||
// .S(1'b0) // 1-bit set input
|
||||
// );
|
||||
//
|
||||
// ODDR2 #(
|
||||
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
|
||||
// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
||||
// ) ODDR2_CLK2 (
|
||||
// .Q(CLK2OUT), // 1-bit DDR output data
|
||||
// .C0(clk2_bufgout), // 1-bit clock input
|
||||
// .C1(~clk2_bufgout), // 1-bit clock input
|
||||
// .CE(1'b1), // 1-bit clock enable input
|
||||
// .D0(1'b1), // 1-bit data input (associated with C0)
|
||||
// .D1(1'b0), // 1-bit data input (associated with C1)
|
||||
// .R(RST), // 1-bit reset input
|
||||
// .S(1'b0) // 1-bit set input
|
||||
// );
|
||||
//
|
||||
// ODDR2 #(
|
||||
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
|
||||
// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
||||
// ) ODDR2_CLK3 (
|
||||
// .Q(CLK3OUT), // 1-bit DDR output data
|
||||
// .C0(clk3_bufgout), // 1-bit clock input
|
||||
// .C1(~clk3_bufgout), // 1-bit clock input
|
||||
// .CE(1'b1), // 1-bit clock enable input
|
||||
// .D0(1'b1), // 1-bit data input (associated with C0)
|
||||
// .D1(1'b0), // 1-bit data input (associated with C1)
|
||||
// .R(RST), // 1-bit reset input
|
||||
// .S(1'b0) // 1-bit set input
|
||||
// );
|
||||
//
|
||||
// ODDR2 #(
|
||||
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
|
||||
// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
||||
// ) ODDR2_CLK4 (
|
||||
// .Q(CLK4OUT), // 1-bit DDR output data
|
||||
// .C0(clk4_bufgout), // 1-bit clock input
|
||||
// .C1(~clk4_bufgout), // 1-bit clock input
|
||||
// .CE(1'b1), // 1-bit clock enable input
|
||||
// .D0(1'b1), // 1-bit data input (associated with C0)
|
||||
// .D1(1'b0), // 1-bit data input (associated with C1)
|
||||
// .R(RST), // 1-bit reset input
|
||||
// .S(1'b0) // 1-bit set input
|
||||
// );
|
||||
//
|
||||
// ODDR2 #(
|
||||
// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
||||
// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1
|
||||
// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
||||
// ) ODDR2_CLK5 (
|
||||
// .Q(CLK5OUT), // 1-bit DDR output data
|
||||
// .C0(clk5_bufgout), // 1-bit clock input
|
||||
// .C1(~clk5_bufgout), // 1-bit clock input
|
||||
// .CE(1'b1), // 1-bit clock enable input
|
||||
// .D0(1'b1), // 1-bit data input (associated with C0)
|
||||
// .D1(1'b0), // 1-bit data input (associated with C1)
|
||||
// .R(RST), // 1-bit reset input
|
||||
// .S(1'b0) // 1-bit set input
|
||||
// );
|
||||
|
||||
// PLL_ADV that reconfiguration will take place on
|
||||
PLL_ADV #(
|
||||
.SIM_DEVICE("SPARTAN6"),
|
||||
.DIVCLK_DIVIDE(1), // 1 to 52
|
||||
|
||||
.BANDWIDTH("LOW"), // "HIGH", "LOW" or "OPTIMIZED"
|
||||
|
||||
// CLKFBOUT stuff
|
||||
.CLKFBOUT_MULT(9),
|
||||
.CLKFBOUT_PHASE(0.0),
|
||||
|
||||
// Set the clock period (ns) of input clocks and reference jitter
|
||||
.REF_JITTER(0.100),
|
||||
.CLKIN1_PERIOD(20.000),
|
||||
.CLKIN2_PERIOD(20.000),
|
||||
|
||||
// CLKOUT parameters:
|
||||
// DIVIDE: (1 to 128)
|
||||
// DUTY_CYCLE: (0.01 to 0.99) - This is dependent on the divide value.
|
||||
// PHASE: (0.0 to 360.0) - This is dependent on the divide value.
|
||||
.CLKOUT0_DIVIDE(16),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0.0),
|
||||
|
||||
.CLKOUT1_DIVIDE(32),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0.0),
|
||||
|
||||
.CLKOUT2_DIVIDE(64),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0.0),
|
||||
|
||||
.CLKOUT3_DIVIDE(128),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0.0),
|
||||
|
||||
.CLKOUT4_DIVIDE(128),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0.0),
|
||||
|
||||
.CLKOUT5_DIVIDE(128),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0.0),
|
||||
|
||||
// Set the compensation
|
||||
.COMPENSATION("SYSTEM_SYNCHRONOUS"),
|
||||
|
||||
// PMCD stuff (not used)
|
||||
.EN_REL("FALSE"),
|
||||
.PLL_PMCD_MODE("FALSE"),
|
||||
.RST_DEASSERT_CLK("CLKIN1")
|
||||
) PLL_ADV_inst (
|
||||
.CLKFBDCM(),
|
||||
.CLKFBOUT(clkfb_bufgin),
|
||||
|
||||
// CLK outputs
|
||||
.CLKOUT0(clk0_bufgin),
|
||||
.CLKOUT1(clk1_bufgin),
|
||||
.CLKOUT2(clk2_bufgin),
|
||||
.CLKOUT3(clk3_bufgin),
|
||||
.CLKOUT4(clk4_bufgin),
|
||||
.CLKOUT5(clk5_bufgin),
|
||||
|
||||
// CLKOUTS to DCM
|
||||
.CLKOUTDCM0(),
|
||||
.CLKOUTDCM1(),
|
||||
.CLKOUTDCM2(),
|
||||
.CLKOUTDCM3(),
|
||||
.CLKOUTDCM4(),
|
||||
.CLKOUTDCM5(),
|
||||
|
||||
// DRP Ports
|
||||
.DO(dout),
|
||||
.DRDY(drdy),
|
||||
.DADDR(daddr),
|
||||
.DCLK(dclk),
|
||||
.DEN(den),
|
||||
.DI(di),
|
||||
.DWE(dwe),
|
||||
|
||||
.LOCKED(locked),
|
||||
.CLKFBIN(clkfb_bufgout),
|
||||
|
||||
// Clock inputs
|
||||
.CLKIN1(CLKIN),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
|
||||
.REL(1'b0),
|
||||
.RST(rst_pll)
|
||||
);
|
||||
|
||||
// PLL_DRP instance that will perform the reconfiguration operations
|
||||
pll_drp PLL_DRP_inst (
|
||||
// Top port connections
|
||||
.SADDR(STATE),
|
||||
.SEN(SSTEP),
|
||||
.RST(RST),
|
||||
.SRDY(SRDY),
|
||||
|
||||
// Input from IBUFG
|
||||
.SCLK(clkin_bufgout),
|
||||
|
||||
// Direct connections to the PLL_ADV
|
||||
.DO(dout),
|
||||
.DRDY(drdy),
|
||||
.LOCKED(locked),
|
||||
.DWE(dwe),
|
||||
.DEN(den),
|
||||
.DADDR(daddr),
|
||||
.DI(di),
|
||||
.DCLK(dclk),
|
||||
.RST_PLL(rst_pll)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -67,7 +67,7 @@ module ps2_mouse_kempston (
|
|||
assign oe_n_kmouse = kmouse_x_req_n & kmouse_y_req_n & kmouse_butt_req_n;
|
||||
|
||||
/*
|
||||
| BSY | x | x | x | ERR | RLS | EXT | PEN |
|
||||
| BSY | 0 | 0 | 0 | ERR | 0 | 0 | DATA_AVL |
|
||||
*/
|
||||
reg reading_mousestatus = 1'b0;
|
||||
always @(posedge clk) begin
|
||||
|
|
|
|||
|
|
@ -24,16 +24,16 @@ module rom (
|
|||
output reg [7:0] dout
|
||||
);
|
||||
|
||||
reg [7:0] mem[0:127];
|
||||
reg [7:0] mem[0:255];
|
||||
integer i;
|
||||
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
|
||||
for (i=0;i<128;i=i+1) begin
|
||||
for (i=0;i<256;i=i+1) begin
|
||||
mem[i] = 8'h00;
|
||||
end
|
||||
$readmemh ("bootloader_hex.txt", mem, 0);
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
dout <= mem[a[6:0]];
|
||||
dout <= mem[a[7:0]];
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -144,7 +144,10 @@ module scancode_to_speccy (
|
|||
row[5] <= 5'b11111;
|
||||
row[6] <= 5'b11111;
|
||||
row[7] <= 5'b11111;
|
||||
state <= IDLE;
|
||||
if (cpuread == 1'b1 || cpuwrite == 1'b1 || rewind == 1'b1)
|
||||
state <= CPUTIME;
|
||||
else
|
||||
state <= IDLE;
|
||||
end
|
||||
IDLE: begin
|
||||
if (key_is_pending == 1'b1) begin
|
||||
|
|
@ -255,7 +258,7 @@ module scancode_to_speccy (
|
|||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
module keyboard_pressed_status (
|
||||
input wire clk,
|
||||
|
|
@ -272,6 +275,8 @@ module keyboard_pressed_status (
|
|||
UPDATING = 2'd1,
|
||||
SCANNING = 2'd2;
|
||||
|
||||
reg keybstat_ne[0:255]; // non extended keymap
|
||||
reg keybstat_ex[0:255]; // extended keymap
|
||||
reg [7:0] addrscan = 8'h00; // keymap bit address
|
||||
reg keypressed_ne = 1'b0; // there is at least one key pressed
|
||||
reg keypressed_ex = 1'b0; // there is at least one extended key pressed
|
||||
|
|
@ -280,52 +285,12 @@ module keyboard_pressed_status (
|
|||
integer i;
|
||||
initial begin
|
||||
kbclean = 1'b1;
|
||||
for (i=0;i<256;i=i+1) begin
|
||||
keybstat_ne[i] = 1'b0;
|
||||
keybstat_ex[i] = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [7:0] addrkeybstat;
|
||||
reg we_key_ne, we_key_ex;
|
||||
reg din_key_ne, din_key_ex;
|
||||
wire dout_key_ne, dout_key_ex;
|
||||
|
||||
keystatmem vector_kb_clean (
|
||||
.clk(clk),
|
||||
.a(addrkeybstat),
|
||||
.we1(we_key_ne),
|
||||
.we2(we_key_ex),
|
||||
.din1(din_key_ne),
|
||||
.din2(din_key_ex),
|
||||
.dout1(dout_key_ne),
|
||||
.dout2(dout_key_ex)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
addrkeybstat = 8'h00;
|
||||
we_key_ne = 1'b0;
|
||||
we_key_ex = 1'b0;
|
||||
din_key_ne = 1'b0;
|
||||
din_key_ex = 1'b0;
|
||||
case (state)
|
||||
RESETTING:
|
||||
begin
|
||||
addrkeybstat = addrscan;
|
||||
we_key_ne = 1'b1;
|
||||
we_key_ex = 1'b1;
|
||||
end
|
||||
UPDATING:
|
||||
begin
|
||||
addrkeybstat = scancode;
|
||||
we_key_ne = ~extended;
|
||||
we_key_ex = extended;
|
||||
din_key_ne = ~released;
|
||||
din_key_ex = ~released;
|
||||
end
|
||||
SCANNING:
|
||||
begin
|
||||
addrkeybstat = addrscan;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst == 1'b1) begin
|
||||
state <= RESETTING;
|
||||
|
|
@ -341,6 +306,8 @@ module keyboard_pressed_status (
|
|||
kbclean <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
keybstat_ne[addrscan] <= 1'b0;
|
||||
keybstat_ex[addrscan] <= 1'b0;
|
||||
addrscan <= addrscan + 8'd1;
|
||||
end
|
||||
end
|
||||
|
|
@ -351,6 +318,10 @@ module keyboard_pressed_status (
|
|||
kbclean <= 1'b0;
|
||||
keypressed_ne <= 1'b0;
|
||||
keypressed_ex <= 1'b0;
|
||||
if (extended == 1'b0)
|
||||
keybstat_ne[scancode] <= ~released;
|
||||
else
|
||||
keybstat_ex[scancode] <= ~released;
|
||||
end
|
||||
SCANNING:
|
||||
begin
|
||||
|
|
@ -363,40 +334,12 @@ module keyboard_pressed_status (
|
|||
keypressed_ex <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
keypressed_ne <= keypressed_ne | dout_key_ne;
|
||||
keypressed_ex <= keypressed_ex | dout_key_ex;
|
||||
keypressed_ne <= keypressed_ne | keybstat_ne[addrscan];
|
||||
keypressed_ex <= keypressed_ex | keybstat_ex[addrscan];
|
||||
end
|
||||
end
|
||||
default:
|
||||
begin
|
||||
state <= SCANNING;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module keystatmem (
|
||||
input wire clk,
|
||||
input wire [7:0] a,
|
||||
input wire we1,
|
||||
input wire we2,
|
||||
input wire din1,
|
||||
input wire din2,
|
||||
output reg dout1,
|
||||
output reg dout2
|
||||
);
|
||||
|
||||
reg keybstat_ne[0:255]; // non extended keymap
|
||||
reg keybstat_ex[0:255]; // extended keymap
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we1 == 1'b1)
|
||||
keybstat_ne[a] <= din1;
|
||||
if (we2 == 1'b1)
|
||||
keybstat_ex[a] <= din2;
|
||||
dout1 <= keybstat_ne[a];
|
||||
dout2 <= keybstat_ex[a];
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 01:22:53 06/15/2015
|
||||
// Design Name:
|
||||
// Module Name: scratch_register
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module scandoubler_ctrl (
|
||||
input wire clk,
|
||||
input wire [15:0] a,
|
||||
input wire iorq_n,
|
||||
input wire wr_n,
|
||||
input wire [7:0] zxuno_addr,
|
||||
input wire zxuno_regrd,
|
||||
input wire zxuno_regwr,
|
||||
input wire [7:0] din,
|
||||
output reg [7:0] dout,
|
||||
output wire oe_n,
|
||||
output wire vga_enable,
|
||||
output wire scanlines_enable,
|
||||
output wire [2:0] freq_option,
|
||||
output wire turbo_enable
|
||||
);
|
||||
|
||||
parameter SCANDBLCTRL = 8'h0B;
|
||||
parameter PRISMSPEEDCTRL = 16'h8e3b; // PRISM speed control: bits D0-D3. We use TURBO=1 if D0-D3>0
|
||||
|
||||
assign oe_n = ~(zxuno_addr == SCANDBLCTRL && zxuno_regrd == 1'b1);
|
||||
|
||||
assign vga_enable = scandblctrl[0];
|
||||
assign scanlines_enable = scandblctrl[1];
|
||||
assign freq_option = scandblctrl[4:2];
|
||||
assign turbo_enable = scandblctrl[7];
|
||||
|
||||
reg [7:0] scandblctrl = 8'h00; // initial value
|
||||
always @(posedge clk) begin
|
||||
if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1)
|
||||
scandblctrl <= din;
|
||||
else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL)
|
||||
scandblctrl[7] <= (din[3:0] == 4'b0000)? 1'b0 : 1'b1;
|
||||
dout <= scandblctrl;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,4 +1,6 @@
|
|||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
|
|
|||
Binary file not shown.
|
After Width: | Height: | Size: 20 KiB |
|
|
@ -27,7 +27,8 @@ module tld_zxuno (
|
|||
output wire [2:0] r,
|
||||
output wire [2:0] g,
|
||||
output wire [2:0] b,
|
||||
output wire csync,
|
||||
output wire hsync,
|
||||
output wire vsync,
|
||||
input wire ear,
|
||||
inout wire clkps2,
|
||||
inout wire dataps2,
|
||||
|
|
@ -60,63 +61,52 @@ module tld_zxuno (
|
|||
input wire joyfire
|
||||
);
|
||||
|
||||
wire wssclk,sysclk,clk14,clk7,clk3d5;
|
||||
// relojes los_relojes_del_sistema (
|
||||
// .CLKIN_IN(clk50mhz),
|
||||
// .CLKDV_OUT(wssclk), // 5MHz
|
||||
// .CLKFX_OUT(sysclk), // 28MHz
|
||||
// .CLKIN_IBUFG_OUT(),
|
||||
// .CLK0_OUT(),
|
||||
// .LOCKED_OUT()
|
||||
// );
|
||||
wire wssclk,sysclk,clk14,clk7,clk3d5,cpuclk;
|
||||
wire CPUContention;
|
||||
wire turbo_enable;
|
||||
wire [2:0] pll_frequency_option;
|
||||
|
||||
assign wssclk = 1'b0; // de momento, sin WSS
|
||||
assign stdn = 1'b0; // fijar norma PAL
|
||||
assign stdnb = 1'b1; // y conectamos reloj PAL
|
||||
assign wssclk = 1'b0; // de momento, sin WSS
|
||||
assign stdn = 1'b0; // fijar norma PAL
|
||||
assign stdnb = 1'b1; // y conectamos reloj PAL
|
||||
|
||||
// pll reloj_maestro
|
||||
// (// Clock in ports
|
||||
// .CLK_IN1 (clk50mhz), // IN
|
||||
// // Clock out ports
|
||||
// .CLK_OUT1 (sysclk), // OUT
|
||||
// // Dynamic reconfiguration ports
|
||||
// .PROGCLK (1'b0), // IN
|
||||
// .PROGDATA (1'b0), // IN
|
||||
// .PROGEN (1'b0), // IN
|
||||
// .PROGDONE ()); // OUT
|
||||
//
|
||||
// reg [2:0] divclk = 3'b000;
|
||||
// always @(posedge sysclk)
|
||||
// divclk <= divclk + 1;
|
||||
// assign clk14 = divclk[0];
|
||||
// assign clk7 = divclk[1];
|
||||
// assign clk3d5 = divclk[2];
|
||||
|
||||
cuatro_relojes relojes_maestros
|
||||
clock_generator relojes_maestros
|
||||
(// Clock in ports
|
||||
.CLK_IN1 (clk50mhz), // IN
|
||||
.CLK_IN1 (clk50mhz),
|
||||
.CPUContention (CPUContention),
|
||||
.pll_option (pll_frequency_option),
|
||||
.turbo_enable (turbo_enable),
|
||||
// Clock out ports
|
||||
.CLK_OUT1 (sysclk) , // OUT
|
||||
.CLK_OUT2 (clk14), // OUT
|
||||
.CLK_OUT3 (clk7), // OUT
|
||||
.CLK_OUT4 (clk3d5)); // OUT
|
||||
|
||||
.CLK_OUT1 (sysclk),
|
||||
.CLK_OUT2 (clk14),
|
||||
.CLK_OUT3 (clk7),
|
||||
.CLK_OUT4 (clk3d5),
|
||||
.cpuclk (cpuclk)
|
||||
);
|
||||
|
||||
wire audio_out;
|
||||
assign audio_out_left = audio_out;
|
||||
assign audio_out_right = audio_out;
|
||||
|
||||
wire [2:0] ri, gi, bi;
|
||||
wire hsync_pal, vsync_pal;
|
||||
|
||||
wire vga_enable, scanlines_enable;
|
||||
|
||||
zxuno la_maquina (
|
||||
.clk(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ahí, para el resto del circuito
|
||||
.wssclk(wssclk), // 5MHz, reloj para el WSS
|
||||
.clk14(clk14),
|
||||
.clk7(clk7),
|
||||
.clk3d5(clk3d5),
|
||||
.cpuclk(cpuclk),
|
||||
.CPUContention(CPUContention),
|
||||
.power_on_reset_n(1'b1), // sólo para simulación. Para implementacion, dejar a 1
|
||||
.r(r),
|
||||
.g(g),
|
||||
.b(b),
|
||||
.csync(csync),
|
||||
.r(ri),
|
||||
.g(gi),
|
||||
.b(bi),
|
||||
.hsync(hsync_pal),
|
||||
.vsync(vsync_pal),
|
||||
.clkps2(clkps2),
|
||||
.dataps2(dataps2),
|
||||
.ear(~ear), // negada porque el hardware tiene un transistor inversor
|
||||
|
|
@ -141,10 +131,32 @@ module tld_zxuno (
|
|||
.joyleft(joyleft),
|
||||
.joyright(joyright),
|
||||
.joyfire(joyfire),
|
||||
|
||||
|
||||
.mouseclk(mouseclk),
|
||||
.mousedata(mousedata)
|
||||
.mousedata(mousedata),
|
||||
|
||||
.vga_enable(vga_enable),
|
||||
.scanlines_enable(scanlines_enable),
|
||||
.freq_option(pll_frequency_option),
|
||||
.turbo_enable(turbo_enable)
|
||||
);
|
||||
|
||||
vga_scandoubler #(.CLKVIDEO(14000)) salida_vga (
|
||||
.clkvideo(clk14),
|
||||
.clkvga(sysclk),
|
||||
.enable_scandoubling(vga_enable),
|
||||
.disable_scaneffect(~scanlines_enable),
|
||||
.ri(ri),
|
||||
.gi(gi),
|
||||
.bi(bi),
|
||||
.hsync_ext_n(hsync_pal),
|
||||
.vsync_ext_n(vsync_pal),
|
||||
.ro(r),
|
||||
.go(g),
|
||||
.bo(b),
|
||||
.hsync(hsync),
|
||||
.vsync(vsync)
|
||||
);
|
||||
|
||||
assign testled = (!flash_cs_n || !sd_cs_n);
|
||||
// reg [21:0] monoestable = 22'hFFFFFF;
|
||||
|
|
@ -156,4 +168,6 @@ module tld_zxuno (
|
|||
// end
|
||||
// assign testled = ~monoestable[21];
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -22,42 +22,48 @@
|
|||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ula_radas (
|
||||
// Clocks
|
||||
// Clocks
|
||||
input wire clk14, // 14MHz master clock
|
||||
input wire clk7,
|
||||
input wire wssclk, // 5MHz WSS clock
|
||||
input wire cpuclk,
|
||||
output wire CPUContention,
|
||||
input wire rst_n, // reset para volver al modo normal
|
||||
|
||||
// CPU interface
|
||||
input wire [15:0] a,
|
||||
input wire mreq_n,
|
||||
input wire iorq_n,
|
||||
input wire rd_n,
|
||||
input wire wr_n,
|
||||
output wire cpuclk,
|
||||
output reg int_n,
|
||||
input wire [7:0] din,
|
||||
// CPU interface
|
||||
input wire [15:0] a,
|
||||
input wire mreq_n,
|
||||
input wire iorq_n,
|
||||
input wire rd_n,
|
||||
input wire wr_n,
|
||||
output wire int_n,
|
||||
input wire [7:0] din,
|
||||
output reg [7:0] dout,
|
||||
|
||||
input wire rasterint_enable,
|
||||
input wire vretraceint_disable,
|
||||
input wire [8:0] raster_line,
|
||||
output wire raster_int_in_progress,
|
||||
|
||||
// VRAM interface
|
||||
output reg [13:0] va, // 16KB videoram
|
||||
output reg [13:0] va, // 16KB videoram
|
||||
input wire [7:0] vramdata,
|
||||
|
||||
// I/O ports
|
||||
input wire ear,
|
||||
input wire [4:0] kbd,
|
||||
input wire ear,
|
||||
input wire [4:0] kbd,
|
||||
output reg mic,
|
||||
output reg spk,
|
||||
input wire issue2_keyboard,
|
||||
input wire timming,
|
||||
input wire [1:0] mode,
|
||||
input wire disable_contention,
|
||||
input wire access_to_contmem,
|
||||
|
||||
// Video
|
||||
output wire [2:0] r,
|
||||
output wire [2:0] g,
|
||||
output wire [2:0] b,
|
||||
output wire csync,
|
||||
output wire [2:0] r,
|
||||
output wire [2:0] g,
|
||||
output wire [2:0] b,
|
||||
output wire hsync,
|
||||
output wire vsync,
|
||||
output wire y_n
|
||||
);
|
||||
|
||||
|
|
@ -76,14 +82,21 @@ module ula_radas (
|
|||
// Counters from sync module
|
||||
wire [8:0] hc;
|
||||
wire [8:0] vc;
|
||||
|
||||
// Signal when the vertical counter is in the line that we use to make the INT signal
|
||||
wire in_int_line;
|
||||
|
||||
reg clkhalf14 = 1'b0;
|
||||
always @(posedge clk14)
|
||||
clkhalf14 <= ~clkhalf14;
|
||||
|
||||
pal_sync_generator_sinclair syncs (
|
||||
pal_sync_generator syncs (
|
||||
.clk(clk7),
|
||||
.timming(timming),
|
||||
.mode(mode),
|
||||
.rasterint_enable(rasterint_enable),
|
||||
.vretraceint_disable(vretraceint_disable),
|
||||
.raster_line(raster_line),
|
||||
.raster_int_in_progress(raster_int_in_progress),
|
||||
.ri(ri),
|
||||
.gi(gi),
|
||||
.bi(bi),
|
||||
|
|
@ -92,24 +105,11 @@ module ula_radas (
|
|||
.ro(r),
|
||||
.go(g),
|
||||
.bo(b),
|
||||
.csync(csync)
|
||||
.hsync(hsync),
|
||||
.vsync(vsync),
|
||||
.int_n(int_n)
|
||||
);
|
||||
|
||||
// pal_sync_generator_progressive syncs (
|
||||
// .clk(clk7),
|
||||
// .wssclk(wssclk),
|
||||
// .ri(ri),
|
||||
// .gi(gi),
|
||||
// .bi(bi),
|
||||
// .hcnt(hc),
|
||||
// .vcnt(vc),
|
||||
// .ro(r),
|
||||
// .go(g),
|
||||
// .bo(b),
|
||||
// .csync(csync)
|
||||
// );
|
||||
|
||||
|
||||
///////////////////////////////////////////////
|
||||
// ULA datapath
|
||||
///////////////////////////////////////////////
|
||||
|
|
@ -500,16 +500,7 @@ module ula_radas (
|
|||
end
|
||||
end
|
||||
end
|
||||
|
||||
// INT generation
|
||||
always @* begin
|
||||
if (vc==BVSYNC && hc>=2 && hc<=65) // 32 T-states INT pulse width
|
||||
int_n = 1'b0;
|
||||
else
|
||||
int_n = 1'b1;
|
||||
end
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// AUXILIARY SIGNALS FOR CONTENTION CONTROL
|
||||
///////////////////////////////////
|
||||
|
|
@ -598,6 +589,8 @@ module ula_radas (
|
|||
CancelContention <= 1'b0;
|
||||
end
|
||||
|
||||
assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0];
|
||||
//assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0];
|
||||
|
||||
assign CPUContention = (~(MayContend_n | CauseContention_n | CancelContention));
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,175 @@
|
|||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:57:54 11/09/2015
|
||||
// Design Name:
|
||||
// Module Name: vga_scandoubler
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module vga_scandoubler (
|
||||
input wire clkvideo,
|
||||
input wire clkvga,
|
||||
input wire enable_scandoubling,
|
||||
input wire disable_scaneffect, // 1 to disable scanlines
|
||||
input wire [2:0] ri,
|
||||
input wire [2:0] gi,
|
||||
input wire [2:0] bi,
|
||||
input wire hsync_ext_n,
|
||||
input wire vsync_ext_n,
|
||||
output reg [2:0] ro,
|
||||
output reg [2:0] go,
|
||||
output reg [2:0] bo,
|
||||
output reg hsync,
|
||||
output reg vsync
|
||||
);
|
||||
|
||||
parameter [31:0] CLKVIDEO = 12000;
|
||||
|
||||
// http://www.epanorama.net/faq/vga2rgb/calc.html
|
||||
// SVGA 800x600
|
||||
// HSYNC = 3.36us VSYNC = 114.32us
|
||||
|
||||
parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000;
|
||||
parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000;
|
||||
|
||||
reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
|
||||
reg [9:0] totalhor = 10'd0;
|
||||
|
||||
// Para generar scanlines:
|
||||
wire [2:0] rout, gout, bout;
|
||||
reg scaneffect = 1'b0;
|
||||
wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : {1'b0, rout[2:1]};
|
||||
wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : {1'b0, gout[2:1]};
|
||||
wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : {1'b0, bout[2:1]};
|
||||
|
||||
// Memoria de doble puerto que guarda la información de dos scans
|
||||
// Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
|
||||
// puntos en negro que se pintan durante el HBlank
|
||||
vgascanline_dport memscan (
|
||||
.clk(clkvga),
|
||||
.addrwrite(addrvideo),
|
||||
.addrread(addrvga),
|
||||
.we(1'b1),
|
||||
.din({ri,gi,bi}),
|
||||
.dout({rout,gout,bout})
|
||||
);
|
||||
|
||||
// Voy alternativamente escribiendo en una mitad o en otra del scan buffer
|
||||
// Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
|
||||
// En "totalhor" mido el número de ciclos de reloj que hay en un scan
|
||||
always @(posedge clkvideo) begin
|
||||
if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
|
||||
totalhor <= addrvideo[9:0];
|
||||
addrvideo <= {~addrvideo[10],10'b0000000000};
|
||||
end
|
||||
else
|
||||
addrvideo <= addrvideo + 11'd1;
|
||||
end
|
||||
|
||||
// Recorro el scanbuffer al doble de velocidad, generando direcciones para
|
||||
// el scan buffer. Cada vez que el video original ha terminado una linea,
|
||||
// cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no
|
||||
// estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer
|
||||
// desde el mismo origen
|
||||
// Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que
|
||||
// uso después para mostrar los píxeles a su brillo nominal, o con su brillo
|
||||
// reducido para un efecto chachi de scanlines en la VGA
|
||||
always @(posedge clkvga) begin
|
||||
if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
|
||||
addrvga <= {~addrvga[10],10'b000000000};
|
||||
scaneffect <= ~scaneffect;
|
||||
end
|
||||
else if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
|
||||
addrvga <= {addrvga[10], 10'b000000000};
|
||||
scaneffect <= ~scaneffect;
|
||||
end
|
||||
else
|
||||
addrvga <= addrvga + 11'd1;
|
||||
end
|
||||
|
||||
// El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo
|
||||
// del barrido de un scanline
|
||||
reg hsync_vga, vsync_vga;
|
||||
|
||||
always @* begin
|
||||
if (addrvga[9:0] < HSYNC_COUNT[9:0])
|
||||
hsync_vga = 1'b0;
|
||||
else
|
||||
hsync_vga = 1'b1;
|
||||
end
|
||||
|
||||
// El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de
|
||||
// bajada de la señal de sincronismo vertical original
|
||||
reg [15:0] cntvsync = 16'hFFFF;
|
||||
initial vsync_vga = 1'b1;
|
||||
always @(posedge clkvga) begin
|
||||
if (vsync_ext_n == 1'b0) begin
|
||||
if (cntvsync == 16'hFFFF) begin
|
||||
cntvsync <= 16'd0;
|
||||
vsync_vga <= 1'b0;
|
||||
end
|
||||
else if (cntvsync != 16'hFFFE) begin
|
||||
if (cntvsync == VSYNC_COUNT[15:0]) begin
|
||||
vsync_vga <= 1'b1;
|
||||
cntvsync <= 16'hFFFE;
|
||||
end
|
||||
else
|
||||
cntvsync <= cntvsync + 16'd1;
|
||||
end
|
||||
end
|
||||
else if (vsync_ext_n == 1'b1)
|
||||
cntvsync <= 16'hFFFF;
|
||||
end
|
||||
|
||||
always @* begin
|
||||
if (enable_scandoubling == 1'b0) begin // 15kHz output
|
||||
ro = ri;
|
||||
go = gi;
|
||||
bo = bi;
|
||||
hsync = hsync_ext_n & vsync_ext_n;
|
||||
vsync = 1'b1;
|
||||
end
|
||||
else begin // VGA output
|
||||
ro = ro_vga;
|
||||
go = go_vga;
|
||||
bo = bo_vga;
|
||||
hsync = hsync_vga;
|
||||
vsync = vsync_vga;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// Una memoria de doble puerto: uno para leer, y otro para
|
||||
// escribir. Es de 2048 direcciones: 1024 se emplean para
|
||||
// guardar un scan, y otros 1024 para el siguiente scan
|
||||
module vgascanline_dport (
|
||||
input wire clk,
|
||||
input wire [10:0] addrwrite,
|
||||
input wire [10:0] addrread,
|
||||
input wire we,
|
||||
input wire [8:0] din,
|
||||
output reg [8:0] dout
|
||||
);
|
||||
|
||||
reg [8:0] scan[0:2047]; // two scanlines
|
||||
always @(posedge clk) begin
|
||||
dout <= scan[addrread];
|
||||
if (we == 1'b1)
|
||||
scan[addrwrite] <= din;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
|
|
@ -23,67 +23,93 @@
|
|||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_zxuno.bgn" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="tld_zxuno.bit" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="tld_zxuno.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="tld_zxuno.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="tld_zxuno.drc" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="tld_zxuno.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_zxuno.ncd" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="tld_zxuno.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="tld_zxuno.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="tld_zxuno.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="tld_zxuno.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="tld_zxuno.par" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="tld_zxuno.pcf" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tld_zxuno.prj"/>
|
||||
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="tld_zxuno.ptwx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="tld_zxuno.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="tld_zxuno.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="tld_zxuno.twr" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="tld_zxuno.twx" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="tld_zxuno.unroutes" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_zxuno.ut" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_XPI" xil_pn:name="tld_zxuno.xpi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="tld_zxuno.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_zxuno_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_NCD" xil_pn:name="tld_zxuno_guide.ncd" xil_pn:origination="imported"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_zxuno_map.map" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_zxuno_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_zxuno_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="tld_zxuno_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="tld_zxuno_pad.csv" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="tld_zxuno_pad.txt" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_par.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_zxuno_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="tld_zxuno_summary.xml"/>
|
||||
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="tld_zxuno_usage.xml"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3524997284752945764" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3524997284752945764" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7188828471653365900" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5917024721248158123" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9129001642772221986" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9129001642772221986" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720323" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="9132046586730190230" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524535" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7860242836324982453" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720546" xil_pn:in_ck="3594304594023129945" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-841030919764162094" xil_pn:start_ts="1433720323">
|
||||
<transform xil_pn:end_ts="1461524679" xil_pn:in_ck="6215721973682195225" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-9197728575697027104" xil_pn:start_ts="1461524535">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_zxuno.cmd_log"/>
|
||||
<outfile xil_pn:name="tld_zxuno.lso"/>
|
||||
<outfile xil_pn:name="tld_zxuno.ngc"/>
|
||||
<outfile xil_pn:name="tld_zxuno.ngr"/>
|
||||
|
|
@ -91,35 +117,74 @@
|
|||
<outfile xil_pn:name="tld_zxuno.stx"/>
|
||||
<outfile xil_pn:name="tld_zxuno.syr"/>
|
||||
<outfile xil_pn:name="tld_zxuno.xst"/>
|
||||
<outfile xil_pn:name="tld_zxuno_envsettings.html"/>
|
||||
<outfile xil_pn:name="tld_zxuno_summary.html"/>
|
||||
<outfile xil_pn:name="tld_zxuno_xst.xrpt"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720547" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8119187138760779895" xil_pn:start_ts="1433720546">
|
||||
<transform xil_pn:end_ts="1461524679" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8119187138760779895" xil_pn:start_ts="1461524679">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720559" xil_pn:in_ck="6001021794932523067" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5213230963878834957" xil_pn:start_ts="1433720547">
|
||||
<transform xil_pn:end_ts="1461524700" xil_pn:in_ck="6001021794932523067" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1980932678471234324" xil_pn:start_ts="1461524679">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_zxuno.bld"/>
|
||||
<outfile xil_pn:name="tld_zxuno.cmd_log"/>
|
||||
<outfile xil_pn:name="tld_zxuno.ngd"/>
|
||||
<outfile xil_pn:name="tld_zxuno_ngdbuild.xrpt"/>
|
||||
<outfile xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1433720562" xil_pn:in_ck="6001021794932523068" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1827537523135263760" xil_pn:start_ts="1433720559">
|
||||
<status xil_pn:value="FailedRun"/>
|
||||
<transform xil_pn:end_ts="1461524844" xil_pn:in_ck="6001021794932523068" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2813566960618702639" xil_pn:start_ts="1461524700">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_zxuno.pcf"/>
|
||||
<outfile xil_pn:name="tld_zxuno_map.map"/>
|
||||
<outfile xil_pn:name="tld_zxuno_map.mrp"/>
|
||||
<outfile xil_pn:name="tld_zxuno_map.ncd"/>
|
||||
<outfile xil_pn:name="tld_zxuno_map.ngm"/>
|
||||
<outfile xil_pn:name="tld_zxuno_map.xrpt"/>
|
||||
<outfile xil_pn:name="tld_zxuno_summary.xml"/>
|
||||
<outfile xil_pn:name="tld_zxuno_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1461524933" xil_pn:in_ck="2351177188178857301" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5773473110588446613" xil_pn:start_ts="1461524844">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_zxuno.ncd"/>
|
||||
<outfile xil_pn:name="tld_zxuno.pad"/>
|
||||
<outfile xil_pn:name="tld_zxuno.par"/>
|
||||
<outfile xil_pn:name="tld_zxuno.ptwx"/>
|
||||
<outfile xil_pn:name="tld_zxuno.unroutes"/>
|
||||
<outfile xil_pn:name="tld_zxuno.xpi"/>
|
||||
<outfile xil_pn:name="tld_zxuno_pad.csv"/>
|
||||
<outfile xil_pn:name="tld_zxuno_pad.txt"/>
|
||||
<outfile xil_pn:name="tld_zxuno_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1461525279" xil_pn:in_ck="-3822709731627043894" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-8005339552791582649" xil_pn:start_ts="1461525195">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_zxuno.bgn"/>
|
||||
<outfile xil_pn:name="tld_zxuno.drc"/>
|
||||
<outfile xil_pn:name="tld_zxuno.ut"/>
|
||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1461524933" xil_pn:in_ck="6001021794932522936" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1461524903">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_zxuno.twr"/>
|
||||
<outfile xil_pn:name="tld_zxuno.twx"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
|
|
|
|||
|
|
@ -27,13 +27,16 @@ module zxuno (
|
|||
input wire clk14,
|
||||
input wire clk7,
|
||||
input wire clk3d5,
|
||||
input wire cpuclk,
|
||||
output wire CPUContention,
|
||||
input wire power_on_reset_n,
|
||||
|
||||
// E/S
|
||||
output wire [2:0] r,
|
||||
output wire [2:0] g,
|
||||
output wire [2:0] b,
|
||||
output wire csync,
|
||||
output wire hsync,
|
||||
output wire vsync,
|
||||
inout wire clkps2,
|
||||
inout wire dataps2,
|
||||
input wire ear,
|
||||
|
|
@ -62,10 +65,16 @@ module zxuno (
|
|||
input wire joyleft,
|
||||
input wire joyright,
|
||||
input wire joyfire,
|
||||
|
||||
|
||||
// MOUSE
|
||||
inout wire mouseclk,
|
||||
inout wire mousedata
|
||||
inout wire mousedata,
|
||||
|
||||
// SCANDOUBLER CTRL
|
||||
output wire vga_enable,
|
||||
output wire scanlines_enable,
|
||||
output wire [2:0] freq_option,
|
||||
output wire turbo_enable
|
||||
);
|
||||
|
||||
// Señales de la CPU
|
||||
|
|
@ -74,7 +83,6 @@ module zxuno (
|
|||
wire [15:0] cpuaddr;
|
||||
wire [7:0] cpudin;
|
||||
wire [7:0] cpudout;
|
||||
wire cpuclk;
|
||||
wire [7:0] ula_dout;
|
||||
|
||||
// Señales acceso RAM por parte de la ULA
|
||||
|
|
@ -128,7 +136,7 @@ module zxuno (
|
|||
wire [4:0] kbdcol_to_ula;
|
||||
|
||||
// Configuración ULA
|
||||
wire timming_ula;
|
||||
wire [1:0] timing_mode;
|
||||
wire issue2_keyboard;
|
||||
wire disable_contention;
|
||||
wire access_to_screen;
|
||||
|
|
@ -140,6 +148,18 @@ module zxuno (
|
|||
// Scratch register
|
||||
wire oe_n_scratch;
|
||||
wire [7:0] scratch_dout;
|
||||
|
||||
// Scandoubler control
|
||||
wire [7:0] scndblctrl_dout;
|
||||
wire oe_n_scndblctrl;
|
||||
|
||||
// Raster INT control
|
||||
wire rasterint_enable;
|
||||
wire vretraceint_disable;
|
||||
wire [8:0] raster_line;
|
||||
wire raster_int_in_progress;
|
||||
wire [7:0] rasterint_dout;
|
||||
wire oe_n_rasterint;
|
||||
|
||||
// NMI events
|
||||
wire [7:0] nmievents_dout;
|
||||
|
|
@ -153,6 +173,9 @@ module zxuno (
|
|||
wire [7:0] mousestatus_dout;
|
||||
wire oe_n_kmouse, oe_n_mousedata, oe_n_mousestatus;
|
||||
|
||||
// Multiboot
|
||||
wire boot_second_core = user_toggles[1]; // KB triggered booting
|
||||
|
||||
// Asignación de dato para la CPU segun la decodificación de todos los dispositivos
|
||||
// conectados a ella.
|
||||
assign cpudin = (oe_n_romyram==1'b0)? memory_dout :
|
||||
|
|
@ -165,10 +188,12 @@ module zxuno (
|
|||
(oe_n_coreid==1'b0)? coreid_dout :
|
||||
(oe_n_keymap==1'b0)? keymap_dout :
|
||||
(oe_n_scratch==1'b0)? scratch_dout :
|
||||
(oe_n_scndblctrl==1'b0)? scndblctrl_dout :
|
||||
(oe_n_nmievents==1'b0)? nmievents_dout :
|
||||
(oe_n_kmouse==1'b0)? kmouse_dout :
|
||||
(oe_n_mousedata==1'b0)? mousedata_dout :
|
||||
(oe_n_mousestatus==1'b0)? mousestatus_dout :
|
||||
(oe_n_rasterint==1'b0)? rasterint_dout :
|
||||
ula_dout;
|
||||
|
||||
tv80n_wrapper el_z80 (
|
||||
|
|
@ -197,6 +222,8 @@ module zxuno (
|
|||
.clk14(clk14), // 14MHz master clock
|
||||
.clk7(clk7),
|
||||
.wssclk(wssclk), // 5MHz WSS clock
|
||||
.cpuclk(cpuclk),
|
||||
.CPUContention(CPUContention),
|
||||
.rst_n(mrst_n & rst_n & power_on_reset_n),
|
||||
|
||||
// CPU interface
|
||||
|
|
@ -206,10 +233,13 @@ module zxuno (
|
|||
.iorq_n(iorq_n),
|
||||
.rd_n(rd_n),
|
||||
.wr_n(wr_n),
|
||||
.cpuclk(cpuclk),
|
||||
.int_n(int_n),
|
||||
.din(cpudout),
|
||||
.dout(ula_dout),
|
||||
.rasterint_enable(rasterint_enable),
|
||||
.vretraceint_disable(vretraceint_disable),
|
||||
.raster_line(raster_line),
|
||||
.raster_int_in_progress(raster_int_in_progress),
|
||||
|
||||
// VRAM interface
|
||||
.va(vram_addr), // 16KB videoram
|
||||
|
|
@ -217,18 +247,19 @@ module zxuno (
|
|||
|
||||
// I/O ports
|
||||
.ear(ear),
|
||||
.mic(mic),
|
||||
.spk(spk),
|
||||
.mic(mic),
|
||||
.spk(spk),
|
||||
.kbd(kbdcol_to_ula),
|
||||
.issue2_keyboard(issue2_keyboard),
|
||||
.timming(timming_ula),
|
||||
.disable_contention(disable_contention),
|
||||
.issue2_keyboard(issue2_keyboard),
|
||||
.mode(timing_mode),
|
||||
.disable_contention(disable_contention),
|
||||
|
||||
// Video
|
||||
.r(r),
|
||||
.g(g),
|
||||
.b(b),
|
||||
.csync(csync)
|
||||
.hsync(hsync),
|
||||
.vsync(vsync)
|
||||
);
|
||||
|
||||
zxunoregs addr_reg_zxuno (
|
||||
|
|
@ -248,7 +279,7 @@ module zxuno (
|
|||
);
|
||||
|
||||
flash_and_sd cacharros_con_spi (
|
||||
.clk(clk),
|
||||
.clk(clk14),
|
||||
.a(cpuaddr),
|
||||
.iorq_n(iorq_n),
|
||||
.rd_n(rd_n),
|
||||
|
|
@ -297,7 +328,7 @@ module zxuno (
|
|||
.vramaddr(vram_addr),
|
||||
.vramdout(vram_dout),
|
||||
.issue2_keyboard_enabled(issue2_keyboard),
|
||||
.timming_ula(timming_ula),
|
||||
.timing_mode(timing_mode),
|
||||
.disable_contention(disable_contention),
|
||||
.access_to_screen(access_to_screen),
|
||||
|
||||
|
|
@ -380,6 +411,38 @@ module zxuno (
|
|||
.oe_n(oe_n_scratch)
|
||||
);
|
||||
|
||||
scandoubler_ctrl control_scandoubler (
|
||||
.clk(clk),
|
||||
.a(cpuaddr),
|
||||
.iorq_n(iorq_n),
|
||||
.wr_n(wr_n),
|
||||
.zxuno_addr(zxuno_addr),
|
||||
.zxuno_regrd(zxuno_regrd),
|
||||
.zxuno_regwr(zxuno_regwr),
|
||||
.din(cpudout),
|
||||
.dout(scndblctrl_dout),
|
||||
.oe_n(oe_n_scndblctrl),
|
||||
.vga_enable(vga_enable),
|
||||
.scanlines_enable(scanlines_enable),
|
||||
.freq_option(freq_option),
|
||||
.turbo_enable(turbo_enable)
|
||||
);
|
||||
|
||||
rasterint_ctrl control_rasterint (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n & mrst_n & power_on_reset_n),
|
||||
.zxuno_addr(zxuno_addr),
|
||||
.zxuno_regrd(zxuno_regrd),
|
||||
.zxuno_regwr(zxuno_regwr),
|
||||
.din(cpudout),
|
||||
.dout(rasterint_dout),
|
||||
.oe_n(oe_n_rasterint),
|
||||
.rasterint_enable(rasterint_enable),
|
||||
.vretraceint_disable(vretraceint_disable),
|
||||
.raster_line(raster_line),
|
||||
.raster_int_in_progress(raster_int_in_progress)
|
||||
);
|
||||
|
||||
nmievents nmi_especial_de_antonio (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n & mrst_n & power_on_reset_n),
|
||||
|
|
@ -421,6 +484,17 @@ module zxuno (
|
|||
.oe_n_mousestatus(oe_n_mousestatus)
|
||||
);
|
||||
|
||||
multiboot el_multiboot (
|
||||
.clk(clk),
|
||||
.clk_icap(clk),
|
||||
.rst_n(rst_n & mrst_n & power_on_reset_n),
|
||||
.kb_boot_core(boot_second_core),
|
||||
.zxuno_addr(zxuno_addr),
|
||||
.zxuno_regwr(zxuno_regwr),
|
||||
.din(cpudout)
|
||||
);
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// AY-3-8912 SOUND
|
||||
///////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -9,159 +9,179 @@
|
|||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="tb_ula.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="audio_management.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
|
||||
</file>
|
||||
<file xil_pn:name="dp_memory.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="T80.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="T80_ALU.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="T80_MCode.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="T80_Pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="T80_Reg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="T80a.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="tld_zxuno.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_to_t80_wrapper.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
|
||||
</file>
|
||||
<file xil_pn:name="YM2149_linmix.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="zxuno.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="pines_zxuno.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
|
||||
</file>
|
||||
<file xil_pn:name="lut.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="tb_zxuno.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="15"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="15"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="zxunoregs.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="flash_spi.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
|
||||
</file>
|
||||
<file xil_pn:name="memory.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
|
||||
</file>
|
||||
<file xil_pn:name="rom.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="tb_spi.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="21"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="21"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
|
||||
</file>
|
||||
<file xil_pn:name="ula_radas.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="turbosound.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="pal_sync_generator_sinclair.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="relojes_pll.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2_keyb.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2_port.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="scancode_to_speccy.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="joystick_protocols.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
|
||||
</file>
|
||||
<file xil_pn:name="coreid.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
|
||||
</file>
|
||||
<file xil_pn:name="scratch_register.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
|
||||
</file>
|
||||
<file xil_pn:name="nmievents.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
|
||||
</file>
|
||||
<file xil_pn:name="cuatro_relojes.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2_mouse_kempston.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2mouse_to_kmouse.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="multiboot.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
|
||||
</file>
|
||||
<file xil_pn:name="vga_scandoubler.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
|
||||
</file>
|
||||
<file xil_pn:name="pines_zxuno.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="scandoubler_ctrl.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
|
||||
</file>
|
||||
<file xil_pn:name="pll_drp.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="pll_top.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
|
||||
</file>
|
||||
<file xil_pn:name="pal_sync_generator.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="control_rasterint.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
|
|
@ -174,6 +194,7 @@
|
|||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
|
|
@ -190,7 +211,7 @@
|
|||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
|
@ -198,7 +219,7 @@
|
|||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -216,32 +237,35 @@
|
|||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -258,7 +282,6 @@
|
|||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -269,7 +292,7 @@
|
|||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
|
|
@ -291,13 +314,15 @@
|
|||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -308,6 +333,7 @@
|
|||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
|
|
@ -342,7 +368,7 @@
|
|||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="-infer_ramb8 No" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="tld_zxuno" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -357,7 +383,7 @@
|
|||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="tld_zxuno_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="tld_zxuno_timesim.v" xil_pn:valueState="default"/>
|
||||
|
|
@ -369,7 +395,6 @@
|
|||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
|
|
@ -398,9 +423,8 @@
|
|||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
|
@ -417,7 +441,7 @@
|
|||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="50" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -440,13 +464,14 @@
|
|||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -467,7 +492,7 @@
|
|||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="A:/ZZ/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
|
|
@ -500,9 +525,7 @@
|
|||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/tld_zxuno" xil_pn:name="pines_zxuno.ucf"/>
|
||||
</bindings>
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
|
|
@ -513,6 +536,7 @@
|
|||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
<file xil_pn:name="pll_drp_func.h" xil_pn:type="FILE_VERILOG"/>
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
|
|||
Loading…
Reference in New Issue