antoniovillena ca2814fb53 Añado core Kyp		2016-10-02 21:18:17 +02:00
..
genframe.v	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
make.bat	Añado core Kyp	2016-10-02 21:18:17 +02:00
master_clk.v	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
pines_zxuno_Ap.ucf	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
pines_zxuno_v2_v3.ucf	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
pines_zxuno_v4.ucf	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
ps2_port.v	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
tld_test_pal_intprog.prj	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00
tld_test_pal_intprog.ut	Cambio lo settings de todos los cores con external clock a 50Mhz	2016-07-16 01:37:30 +02:00
tld_test_pal_intprog.xst	Añado test_pal_interlaced_progressive	2016-07-10 16:32:58 +02:00