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antoniovillena 2016-07-15 02:32:15 +02:00
parent c34e051739
commit 77d90edde8
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1129
cores/JupiterAce/T80.vhd
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cores/JupiterAce/T80_ALU.vhd
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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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cores/JupiterAce/T80_MCode.vhd
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cores/JupiterAce/T80_Pack.vhd
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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
SavePC : out std_logic_vector(15 downto 0);
SaveINT : out std_logic_vector(7 downto 0);
RestorePC : in std_logic_vector(15 downto 0);
RestoreINT : in std_logic_vector(7 downto 0);
RestorePC_n : in std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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cores/JupiterAce/T80_Reg.vhd
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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

286
cores/JupiterAce/T80a.vhd
View File

@ -1,286 +0,0 @@
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0);
SavePC : out std_logic_vector(15 downto 0);
SaveINT : out std_logic_vector(7 downto 0);
RestorePC : in std_logic_vector(15 downto 0);
RestoreINT : in std_logic_vector(7 downto 0);
RestorePC_n : in std_logic
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
SavePC => SavePC,
SaveINT => SaveINT,
RestorePC => RestorePC,
RestoreINT => RestoreINT,
RestorePC_n => RestorePC_n );
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
MREQ <= '0';
end if;
end if;
end if;
end process;
-- IORQ_n_i uses a different timming than MREQ.
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
IORQ_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" then
if TState = "001" then
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
IORQ_n_i <= '1';
end if;
else
if TState = "001" then
IORQ_n_i <= not IORQ;
end if;
if TState = "011" then
IORQ_n_i <= '1';
end if;
end if;
end if;
end process;
end;

67
cores/JupiterAce/fpga_ace.v
View File

@ -22,17 +22,18 @@
//////////////////////////////////////////////////////////////////////////////////
module fpga_ace (
input wire clkram,
input wire clkram,
input wire clk65,
input wire clkcpu,
input wire clkcpu,
input wire reset,
input wire ear,
output wire [7:0] filas,
input wire [4:0] columnas,
output wire video,
output wire sync,
output wire mic,
output wire spk
output wire hsync,
output wire vsync,
output wire mic,
output wire spk
);
// Los buses del Z80
@ -40,24 +41,31 @@ module fpga_ace (
wire [7:0] DoutZ80;
wire [15:0] AZ80;
// Señales de control, direccion y datos de parte de todas las memorias
wire iorq_n, mreq_n, int_n, rd_n, wr_n, wait_n;
wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
wire [7:0] sram_data, cram_data;
wire [9:0] sram_addr, cram_addr;
wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
wire [7:0] sram_data, cram_data;
wire [9:0] sram_addr, cram_addr;
// Señales para la implementación de la habilitación de escritura en ROM
wire enable_write_to_rom;
wire [7:0] dout_modulo_enable_write;
wire modulo_enable_write_oe;
// Copia del bus de direcciones para las filas del teclado
assign filas = AZ80[15:8];
assign filas = AZ80[15:8];
// Multiplexor para asignar un valor al bus de datos de entrada del Z80
assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
(sram_enable == 1'b1)? dout_sram :
(cram_enable == 1'b1)? dout_cram :
(uram_enable == 1'b1)? dout_uram :
(xram_enable == 1'b1)? dout_xram :
(eram_enable == 1'b1)? dout_eram :
(data_from_jace_oe == 1'b1)? data_from_jace :
sram_data | cram_data; // By default, this is what the data bus sees
// Multiplexor para asignar un valor al bus de datos de entrada del Z80
assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
(sram_enable == 1'b1)? dout_sram :
(cram_enable == 1'b1)? dout_cram :
(uram_enable == 1'b1)? dout_uram :
(xram_enable == 1'b1)? dout_xram :
(eram_enable == 1'b1)? dout_eram :
(modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
(data_from_jace_oe == 1'b1)? data_from_jace :
sram_data | cram_data; // By default, this is what the data bus sees
// Memoria del equipo
ram1k_dualport sram (
@ -112,8 +120,11 @@ module fpga_ace (
/* La ROM */
rom the_rom(
.clk(clkram),
.ce(rom_enable),
.a(AZ80[12:0]),
.dout(dout_rom)
.din(DoutZ80),
.dout(dout_rom),
.we(~wr_n & enable_write_to_rom)
);
/* La CPU */
@ -155,7 +166,21 @@ module fpga_ace (
.spk(spk),
.mic(mic),
.video(video),
.csync(sync)
.hsync_pal(hsync),
.vsync_pal(vsync)
);
io_write_to_rom modulo_habilitador_escrituras (
.clk(clk65),
.a(AZ80),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(DoutZ80),
.dout(dout_modulo_enable_write),
.dout_oe(modulo_enable_write_oe),
.enable_write_to_rom(enable_write_to_rom)
);
endmodule

8
cores/JupiterAce/jace_logic.v
View File

@ -50,7 +50,8 @@ module jace_logic (
output reg spk,
output reg mic,
output wire video,
output wire csync
output wire hsync_pal,
output wire vsync_pal
);
initial begin
@ -62,6 +63,7 @@ module jace_logic (
reg [8:0] cntpix = 9'd0;
reg [8:0] cntscn = 9'd0;
wire [17:0] cnt = {cntscn, cntpix};
always @(posedge clk) begin
if (cntpix != 9'd415)
cntpix <= cntpix + 9'd1;
@ -91,7 +93,9 @@ module jace_logic (
hsync = 1'b1;
end
assign csync = hsync & vsync;
//assign csync = hsync & vsync;
assign hsync_pal = hsync;
assign vsync_pal = vsync;
reg viden; // VIDEN signal in schematic
always @* begin

4
cores/JupiterAce/jupiter_ace.prj
View File

@ -3,11 +3,13 @@ verilog work "tv80_mcode.v"
verilog work "tv80_alu.v"
verilog work "tv80_core.v"
verilog work "tv80n.v"
verilog work "rom.v"
verilog work "ps2_port.v"
verilog work "memorias.v"
verilog work "jace_logic.v"
verilog work "io_write_to_rom.v"
verilog work "vga_scandoubler.v"
verilog work "relojes.v"
verilog work "multiboot.v"
verilog work "keyboard_for_ace.v"
verilog work "fpga_ace.v"
verilog work "jupiter_ace.v"

72
cores/JupiterAce/jupiter_ace.v
View File

@ -6,7 +6,7 @@
//
// Create Date: 17:18:12 11/07/2015
// Design Name:
// Module Name: tld_jace_spartan6
// Module Name: jupiter_ace
// Project Name:
// Target Devices:
// Tool versions:
@ -29,24 +29,32 @@ module jupiter_ace (
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync,
output wire hsync,
output wire vsync,
output wire stdn,
output wire stdnb
output wire stdnb,
///// SRAM pins (just to get the current video output setting) ////////////
output wire [20:0] sram_addr,
input wire [7:0] sram_data,
output wire sram_we_n
);
wire clkram; // 50MHz (maybe less if needed) to clock internal RAM/ROM
wire clkram; // 26.666666MHz to clock internal RAM/ROM
wire clk65; // 6.5MHz main frequency Jupiter ACE
wire clkcpu; // CPU CLK
wire clkvga; // Twice the original pixel clock
wire kbd_reset;
wire kbd_mreset;
wire [7:0] kbd_rows;
wire [4:0] kbd_columns;
wire video; // 1-bit video signal (black/white)
// Trivial conversion from B/W video to RGB
assign r = {video,video,1'b0};
assign g = {video,video,1'b0};
assign b = {video,video,1'b0};
// Trivial conversion from B/W video to RGB for the scandoubler
wire pal_hsync, pal_vsync; // inputs to the scandoubler
wire [2:0] ri = {video,video,1'b0};
wire [2:0] gi = {video,video,1'b0};
wire [2:0] bi = {video,video,1'b0};
// Trivial conversion for audio
wire mic,spk;
@ -56,19 +64,27 @@ module jupiter_ace (
// Select PAL
assign stdn = 1'b0; // PAL selection for AD724
assign stdnb = 1'b1; // 4.43MHz crystal selected
// Initial video output settings
reg [7:0] scandblr_reg; // same layout as in the Spectrum core, SCANDBLR_CTRL
// Power-on RESET (8 clocks)
reg [7:0] poweron_reset = 8'h00;
always @(posedge clk65)
assign sram_addr = 21'h008FD5; // magic place where the scandoubler settings have been stored
assign sram_we_n = 1'b1;
always @(posedge clk65) begin
if (poweron_reset == 1'b0)
scandblr_reg <= sram_data;
poweron_reset <= {poweron_reset[6:0],1'b1};
end
cuatro_relojes system_clocks_pll (
.CLK_IN1(clk50mhz),
.CLK_OUT1(clkram), // for driving synch RAM and ROM = 26.6666 MHz
.CLK_OUT2(clk65), // video clock = 6.66666 MHz
.CLK_OUT3(clkcpu), // CPU clock = 0.5 video clock
.CLK_OUT4() // Super CPU clock (just a test)
);
.CLK_OUT1(clkram), // for driving RAM and ROM = 26 MHz
.CLK_OUT2(clkvga), // VGA clock: 2 x video clock
.CLK_OUT3(clk65), // video clock = 6.5 MHz
.CLK_OUT4(clkcpu) // CPU clock = 3.25 MHz
);
fpga_ace the_core (
.clkram(clkram),
@ -79,7 +95,8 @@ module jupiter_ace (
.filas(kbd_rows),
.columnas(kbd_columns),
.video(video),
.sync(csync),
.hsync(pal_hsync),
.vsync(pal_vsync),
.mic(mic),
.spk(spk)
);
@ -91,7 +108,30 @@ module jupiter_ace (
.rows(kbd_rows),
.columns(kbd_columns),
.kbd_reset(kbd_reset),
.kbd_nmi()
.kbd_nmi(),
.kbd_mreset(kbd_mreset)
);
vga_scandoubler #(.CLKVIDEO(6500)) salida_vga (
.clkvideo(clk65),
.clkvga(clkvga),
.enable_scandoubling(scandblr_reg[0]),
.disable_scaneffect(~scandblr_reg[1]),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(pal_hsync),
.vsync_ext_n(pal_vsync),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
multiboot return_to_main_core (
.clk_icap(clkvga),
.mrst_n(kbd_mreset)
);
endmodule

11
cores/JupiterAce/jupiter_ace.xst
View File

@ -2,20 +2,22 @@ set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn jupiter_ace.prj
-infer_ramb8 No
-ofn jupiter_ace
-ofmt NGC
-p xc6slx9-2-tqg144
-top jupiter_ace
-opt_mode Area
-opt_level 1
-opt_mode Speed
-opt_level 2
-power NO
-uc "timings.xcf"
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-write_timing_constraints YES
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
@ -25,8 +27,7 @@ run
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_extract NO
-fsm_style LUT
-ram_extract Yes
-ram_style Auto

66
cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
@ -29,38 +29,38 @@ NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_addr<19>" IOSTANDARD = LVCMOS33;
NET "sram_addr<20>" IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;

68
cores/JupiterAce/jupiter_ace_zxuno_v2_v3.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
@ -29,38 +29,38 @@ NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_addr<19>" IOSTANDARD = LVCMOS33;
NET "sram_addr<20>" IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
@ -86,6 +86,6 @@ NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros

66
cores/JupiterAce/jupiter_ace_zxuno_v4.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
@ -29,38 +29,38 @@ NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;

17
cores/JupiterAce/keyboard_for_ace.v
View File

@ -25,12 +25,14 @@ module keyboard_for_ace(
input wire [7:0] rows,
output wire [4:0] columns,
output reg kbd_reset,
output reg kbd_nmi
output reg kbd_nmi,
output reg kbd_mreset
);
initial begin
kbd_reset = 1'b1;
kbd_nmi = 1'b1;
kbd_mreset = 1'b1;
end
`include "mapa_teclado_es.vh"
@ -85,7 +87,13 @@ module keyboard_for_ace(
shift_pressed <= ~is_released;
`KEY_LCTRL,
`KEY_RCTRL:
ctrl_pressed <= ~is_released;
begin
ctrl_pressed <= ~is_released;
if (is_extended)
matrix[0][1] <= is_released; // Right control = Symbol shift
else
matrix[0][0] <= is_released; // Left control = Caps shift
end
`KEY_LALT:
alt_pressed <= ~is_released;
`KEY_KPPUNTO:
@ -113,7 +121,10 @@ module keyboard_for_ace(
matrix[7][0] <= is_released;
end
`KEY_BKSP:
begin
if (ctrl_pressed && alt_pressed) begin
kbd_mreset <= is_released;
end
else begin
matrix[0][0] <= is_released;
matrix[4][0] <= is_released;
end

22
cores/JupiterAce/memorias.v
View File

@ -20,6 +20,28 @@
//
//////////////////////////////////////////////////////////////////////////////////
module rom (
input wire clk,
input wire ce,
input wire [12:0] a,
input wire we,
input wire [7:0] din,
output reg [7:0] dout
);
reg [7:0] mem[0:8191];
integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
$readmemh ("ace.hex", mem, 0);
end
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
module ram1k (
input wire clk,
input wire ce,

40
cores/JupiterAce/relojes.v
View File

@ -61,7 +61,7 @@ module cuatro_relojes
output wire CLK_OUT4
);
wire clkin1,clkout0,clkout1,clkout2,clkout3;
wire clkin1,clkout0;
// Input buffering
//------------------------------------
IBUFG clkin1_buf
@ -76,47 +76,39 @@ module cuatro_relojes
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_MULT (13),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (15),
.CLKOUT0_DIVIDE (25),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (60),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (120),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_DIVIDE (30),
.CLKOUT3_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.CLKOUT1 (),
.CLKOUT2 (),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.LOCKED (),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
reg [2:0] clkdivider = 3'b000;
always @(posedge clkout0)
clkdivider <= clkdivider + 3'b001;
// Output buffering
//-----------------------------------
@ -124,22 +116,20 @@ module cuatro_relojes
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
.I (clkdivider[0]));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
.I (clkdivider[1]));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
.I (clkdivider[2]));
endmodule

36
cores/JupiterAce/rom.v
View File

@ -1,36 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:12:52 02/09/2014
// Design Name:
// Module Name: rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rom (
input wire clk,
input wire [12:0] a,
output reg [7:0] dout
);
reg [7:0] mem[0:8191];
integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
$readmemh ("ace.hex", mem, 0);
end
always @(posedge clk) begin
dout <= mem[a[12:0]];
end
endmodule

21
cores/JupiterAce/rom8k.asy
View File

@ -1,21 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 rom8k
RECTANGLE Normal 32 32 544 672
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[12:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[7:0]
PINATTR Polarity OUT

33
cores/JupiterAce/rom8k.gise
View File

@ -1,33 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="rom8k.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="rom8k.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="rom8k.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="rom8k.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>

8192
cores/JupiterAce/rom8k.mif
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File diff suppressed because it is too large Load Diff

3
cores/JupiterAce/rom8k.ngc
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File diff suppressed because one or more lines are too long

21
cores/JupiterAce/rom8k.sym
View File

@ -1,21 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="rom8k">
<symboltype>BLOCK</symboltype>
<timestamp>2011-3-23T1:22:54</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[12:0]" />
<pin polarity="Input" x="0" y="144" name="ena" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Output" x="576" y="80" name="douta[7:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">rom8k</text>
<rect width="512" x="32" y="32" height="640" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[12:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[7:0]" />
</graph>
</symbol>

158
cores/JupiterAce/rom8k.v
View File

@ -1,158 +0,0 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file rom8k.v when simulating
// the core, rom8k. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module rom8k(
clka,
ena,
addra,
douta);
input clka;
input ena;
input [12 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("rom8k.mif"),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rom8k is "black_box"
endmodule

65
cores/JupiterAce/rom8k.veo
View File

@ -1,65 +0,0 @@
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
rom8k YourInstanceName (
.clka(clka),
.ena(ena),
.addra(addra), // Bus [12 : 0]
.douta(douta)); // Bus [7 : 0]
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file rom8k.v when simulating
// the core, rom8k. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

93
cores/JupiterAce/rom8k.xco
View File

@ -1,93 +0,0 @@
##############################################################
#
# Xilinx Core Generator version 12.4
# Date: Wed Mar 23 01:23:52 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=.\rom_jace.coe
CSET collision_warnings=ALL
CSET component_name=rom8k
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET load_init_file=true
CSET memory_type=Single_Port_ROM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=0
CSET port_b_clock=0
CSET port_b_enable_rate=0
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=8192
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
GENERATE
# CRC: f60395b6

368
cores/JupiterAce/rom8k.xise
View File

@ -1,368 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="rom8k.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="rom8k.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|rom8k" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="rom8k.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/rom8k" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="rom8k" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="rom8k_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="rom8k_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="rom8k_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="rom8k_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="rom8k" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-23T02:23:57" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FB5288D369F04B859B807E0D8D321ED9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

15
cores/JupiterAce/rom8k_flist.txt
View File

@ -1,15 +0,0 @@
# Output products list for <rom8k>
_xmsgs\pn_parser.xmsgs
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
rom8k.asy
rom8k.gise
rom8k.mif
rom8k.ngc
rom8k.sym
rom8k.v
rom8k.veo
rom8k.xco
rom8k.xise
rom8k_flist.txt
rom8k_xmdf.tcl

84
cores/JupiterAce/rom8k_xmdf.tcl
View File

@ -1,84 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide rom8k_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::rom8k_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::rom8k_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name rom8k
}
# ::rom8k_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::rom8k_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.mif
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom8k_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom8k
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams

37
cores/MasterSystem/src/sms.vhd
View File

@ -6,8 +6,8 @@ entity sms is
port (
clk: in STD_LOGIC;
ram_we_n: out STD_LOGIC;
ram_a: out STD_LOGIC_VECTOR(18 downto 0);
sram_we_n: out STD_LOGIC;
sram_a: out STD_LOGIC_VECTOR(18 downto 0);
ram_d: inout STD_LOGIC_VECTOR(7 downto 0); --Q
-- j1_MDsel: out STD_LOGIC; --Q
@ -171,13 +171,18 @@ architecture Behavioral of sms is
signal rgb_clk: std_logic;
-- signal scanDB: std_logic;
signal scanSWk: std_logic;
signal scanSW: std_logic;
signal j2_tr: std_logic;
signal c0, c1, c2 : std_logic_vector(9 downto 0); --hdmi
signal poweron_reset: unsigned(7 downto 0) := "00000000";
signal scandoubler_ctrl: std_logic_vector(1 downto 0);
signal ram_we_n: std_logic;
signal ram_a: std_logic_vector(18 downto 0);
begin
clock_inst: clock
@ -257,7 +262,7 @@ begin
ps2_clk => ps2_clk,
ps2_data => ps2_data,
scanSW => scanSW,
scanSW => scanSWk,
spi_do => spi_do,
spi_sclk => spi_sclk,
@ -266,6 +271,7 @@ begin
);
led <= not spi_cs_n; --Q
-- led <= scandoubler_ctrl(0); --debug scandblctrl reg.
audio_l <= audio;
audio_r <= audio;
@ -273,6 +279,25 @@ begin
NTSC <= '0';
PAL <= '1';
---- scandlbctrl register detection for video mode initialization at start ----
process (clk_cpu)
begin
if rising_edge(clk_cpu) then
if (poweron_reset < 126) then
scandoubler_ctrl <= ram_d(1 downto 0);
end if;
if poweron_reset < 254 then
poweron_reset <= poweron_reset + 1;
end if;
end if;
end process;
sram_a <= "0001000111111010101" when poweron_reset < 254 else ram_a; --0x8FD5 SRAM (SCANDBLCTRL REG)
sram_we_n <= '1' when poweron_reset < 254 else ram_we_n;
-------------------------------------------------------------------------------
vsync <= vga_vsync when scanSW='1' else '1';
hsync <= vga_hsync when scanSW='1' else rgb_hsync;
@ -286,8 +311,10 @@ begin
x <= vga_x when scanSW='1' else rgb_x;
y <= vga_y when scanSW='1' else rgb_y;
-- sel_pclock <= '1' when scanDB='1' else '0';
sel_pclock <= '1' when scanSW='1' else '0';
-- scanSW <= '1' when scanSWk = '1' else '0';
scanSW <= scandoubler_ctrl(0) xor scanSWk; -- Video mode change via ScrollLock / SCANDBLCTRL reg.
--HDMI

40
cores/MasterSystem/src/sms_zxuno_Ap.ucf
View File

@ -29,25 +29,25 @@ NET "ps2_data" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET ram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33;
NET ram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33;
NET ram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33;
NET ram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33;
NET ram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33;
NET ram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33;
NET ram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33;
NET ram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33;
NET ram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33;
NET ram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33;
NET ram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33;
NET ram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33;
NET ram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33;
NET ram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33;
NET ram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33;
NET ram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33;
NET ram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33;
NET ram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33;
NET ram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33;
NET sram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33;
NET sram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33;
NET sram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33;
NET sram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33;
NET sram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33;
NET sram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33;
NET sram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33;
NET sram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33;
NET sram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33;
NET sram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33;
NET sram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33;
NET sram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33;
NET sram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33;
NET sram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33;
NET sram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33;
NET sram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33;
NET sram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33;
NET sram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33;
NET sram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33;
@ -60,7 +60,7 @@ NET ram_d(5) LOC="P102" | IOSTANDARD = LVCMOS33;
NET ram_d(6) LOC="P101" | IOSTANDARD = LVCMOS33;
NET ram_d(7) LOC="P100" | IOSTANDARD = LVCMOS33;
NET ram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33;
NET sram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33;

157
cores/MasterSystem/src/sms_zxuno_v2.ucf
View File

@ -1,84 +1,97 @@
#UCF para el ZX-UNO v2
NET "CLK" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "CLK" PERIOD=20 ns;
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
# Video output
NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
NET PAL LOC="P67" | IOSTANDARD = LVCMOS33;
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "j1_tr" LOC="P143" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_right" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_left" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_down" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_up" LOC="P142" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
NET ram_a(0) LOC="P115" | IOSTANDARD=LVCMOS33;
NET ram_a(1) LOC="P116" | IOSTANDARD=LVCMOS33;
NET ram_a(2) LOC="P117" | IOSTANDARD=LVCMOS33;
NET ram_a(3) LOC="P119" | IOSTANDARD=LVCMOS33;
NET ram_a(4) LOC="P120" | IOSTANDARD=LVCMOS33;
NET ram_a(5) LOC="P123" | IOSTANDARD=LVCMOS33;
NET ram_a(6) LOC="P126" | IOSTANDARD=LVCMOS33;
NET ram_a(7) LOC="P131" | IOSTANDARD=LVCMOS33;
NET ram_a(8) LOC="P127" | IOSTANDARD=LVCMOS33;
NET ram_a(9) LOC="P124" | IOSTANDARD=LVCMOS33;
NET ram_a(10) LOC="P118" | IOSTANDARD=LVCMOS33;
NET ram_a(11) LOC="P121" | IOSTANDARD=LVCMOS33;
NET ram_a(12) LOC="P133" | IOSTANDARD=LVCMOS33;
NET ram_a(13) LOC="P132" | IOSTANDARD=LVCMOS33;
NET ram_a(14) LOC="P137" | IOSTANDARD=LVCMOS33;
NET ram_a(15) LOC="P140" | IOSTANDARD=LVCMOS33;
NET ram_a(16) LOC="P139" | IOSTANDARD=LVCMOS33;
NET ram_a(17) LOC="P141" | IOSTANDARD=LVCMOS33;
NET ram_a(18) LOC="P138" | IOSTANDARD=LVCMOS33;
# Keyboard and mouse
NET "ps2_clk" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ps2_data" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
NET ram_d(0) LOC="P114" | IOSTANDARD=LVCMOS33;
NET ram_d(1) LOC="P112" | IOSTANDARD=LVCMOS33;
NET ram_d(2) LOC="P111" | IOSTANDARD=LVCMOS33;
NET ram_d(3) LOC="P99" | IOSTANDARD=LVCMOS33;
NET ram_d(4) LOC="P100" | IOSTANDARD=LVCMOS33;
NET ram_d(5) LOC="P101" | IOSTANDARD=LVCMOS33;
NET ram_d(6) LOC="P102" | IOSTANDARD=LVCMOS33;
NET ram_d(7) LOC="P104" | IOSTANDARD=LVCMOS33;
# SRAM
NET sram_a(0) LOC="P115" | IOSTANDARD = LVCMOS33;
NET sram_a(1) LOC="P116" | IOSTANDARD = LVCMOS33;
NET sram_a(2) LOC="P117" | IOSTANDARD = LVCMOS33;
NET sram_a(3) LOC="P119" | IOSTANDARD = LVCMOS33;
NET sram_a(4) LOC="P120" | IOSTANDARD = LVCMOS33;
NET sram_a(5) LOC="P123" | IOSTANDARD = LVCMOS33;
NET sram_a(6) LOC="P126" | IOSTANDARD = LVCMOS33;
NET sram_a(7) LOC="P131" | IOSTANDARD = LVCMOS33;
NET sram_a(8) LOC="P127" | IOSTANDARD = LVCMOS33;
NET sram_a(9) LOC="P124" | IOSTANDARD = LVCMOS33;
NET sram_a(10) LOC="P118" | IOSTANDARD = LVCMOS33;
NET sram_a(11) LOC="P121" | IOSTANDARD = LVCMOS33;
NET sram_a(12) LOC="P133" | IOSTANDARD = LVCMOS33;
NET sram_a(13) LOC="P132" | IOSTANDARD = LVCMOS33;
NET sram_a(14) LOC="P137" | IOSTANDARD = LVCMOS33;
NET sram_a(15) LOC="P140" | IOSTANDARD = LVCMOS33;
NET sram_a(16) LOC="P139" | IOSTANDARD = LVCMOS33;
NET sram_a(17) LOC="P141" | IOSTANDARD = LVCMOS33;
NET sram_a(18) LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_a<19>" IOSTANDARD = LVCMOS33;
#NET "sram_a<20>" IOSTANDARD = LVCMOS33;
NET ram_WE_n LOC="P134" | IOSTANDARD=LVCMOS33;
NET ram_d(0) LOC="P114" | IOSTANDARD = LVCMOS33;
NET ram_d(1) LOC="P112" | IOSTANDARD = LVCMOS33;
NET ram_d(2) LOC="P111" | IOSTANDARD = LVCMOS33;
NET ram_d(3) LOC="P99" | IOSTANDARD = LVCMOS33;
NET ram_d(4) LOC="P100" | IOSTANDARD = LVCMOS33;
NET ram_d(5) LOC="P101" | IOSTANDARD = LVCMOS33;
NET ram_d(6) LOC="P102" | IOSTANDARD = LVCMOS33;
NET ram_d(7) LOC="P104" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P67" | IOSTANDARD=LVCMOS33;
NET PAL LOC="P66" | IOSTANDARD=LVCMOS33;
NET sram_WE_n LOC="P134" | IOSTANDARD = LVCMOS33;
NET "ps2_data" LOC="P97" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "ps2_clk" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
# SD/MMC
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
NET "j1_up" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD = "TMDS_33";

157
cores/MasterSystem/src/sms_zxuno_v3.ucf
View File

@ -1,84 +1,97 @@
#UCF para el ZX-UNO v3
NET "CLK" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20 ns;
NET "led" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "CLK" PERIOD=20 ns;
NET "CLK" LOC="P55" | IOSTANDARD=LVCMOS33;
# Video output
NET "red(2)" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
NET PAL LOC="P67" | IOSTANDARD = LVCMOS33;
NET "led" LOC="P10" | IOSTANDARD=LVCMOS33;
# Sound input/output
NET "audio_l" LOC="P8" | IOSTANDARD = LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "j1_tr" LOC="P39" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "j1_up" LOC="P1" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "vsync" LOC="P85" | IOSTANDARD=LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD=LVCMOS33;
NET "green(0)" LOC="P82" | IOSTANDARD=LVCMOS33;
NET "red(0)" LOC="P88" | IOSTANDARD=LVCMOS33;
NET "blue(0)" LOC="P79" | IOSTANDARD=LVCMOS33;
NET "green(1)" LOC="P83" | IOSTANDARD=LVCMOS33;
NET "red(1)" LOC="P92" | IOSTANDARD=LVCMOS33;
NET "blue(1)" LOC="P80" | IOSTANDARD=LVCMOS33;
NET "green(2)" LOC="P84" | IOSTANDARD=LVCMOS33;
NET "red(2)" LOC="P93" | IOSTANDARD=LVCMOS33;
NET "blue(2)" LOC="P81" | IOSTANDARD=LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD=LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD=LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD=LVCMOS33;
NET "spi_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;
NET "audio_l" LOC="P8" | IOSTANDARD=LVCMOS33;
NET "audio_r" LOC="P9" | IOSTANDARD=LVCMOS33;
NET ram_a(0) LOC="P143" | IOSTANDARD=LVCMOS33;
NET ram_a(1) LOC="P142" | IOSTANDARD=LVCMOS33;
NET ram_a(2) LOC="P141" | IOSTANDARD=LVCMOS33;
NET ram_a(3) LOC="P140" | IOSTANDARD=LVCMOS33;
NET ram_a(4) LOC="P139" | IOSTANDARD=LVCMOS33;
NET ram_a(5) LOC="P104" | IOSTANDARD=LVCMOS33;
NET ram_a(6) LOC="P102" | IOSTANDARD=LVCMOS33;
NET ram_a(7) LOC="P101" | IOSTANDARD=LVCMOS33;
NET ram_a(8) LOC="P100" | IOSTANDARD=LVCMOS33;
NET ram_a(9) LOC="P99" | IOSTANDARD=LVCMOS33;
NET ram_a(10) LOC="P112" | IOSTANDARD=LVCMOS33;
NET ram_a(11) LOC="P114" | IOSTANDARD=LVCMOS33;
NET ram_a(12) LOC="P115" | IOSTANDARD=LVCMOS33;
NET ram_a(13) LOC="P116" | IOSTANDARD=LVCMOS33;
NET ram_a(14) LOC="P117" | IOSTANDARD=LVCMOS33;
NET ram_a(15) LOC="P131" | IOSTANDARD=LVCMOS33;
NET ram_a(16) LOC="P133" | IOSTANDARD=LVCMOS33;
NET ram_a(17) LOC="P134" | IOSTANDARD=LVCMOS33;
NET ram_a(18) LOC="P137" | IOSTANDARD=LVCMOS33;
# Keyboard and mouse
NET "ps2_clk" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ps2_data" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
NET ram_d(0) LOC="P132" | IOSTANDARD=LVCMOS33;
NET ram_d(1) LOC="P126" | IOSTANDARD=LVCMOS33;
NET ram_d(2) LOC="P123" | IOSTANDARD=LVCMOS33;
NET ram_d(3) LOC="P120" | IOSTANDARD=LVCMOS33;
NET ram_d(4) LOC="P119" | IOSTANDARD=LVCMOS33;
NET ram_d(5) LOC="P121" | IOSTANDARD=LVCMOS33;
NET ram_d(6) LOC="P124" | IOSTANDARD=LVCMOS33;
NET ram_d(7) LOC="P127" | IOSTANDARD=LVCMOS33;
# SRAM
NET sram_a(0) LOC="P143" | IOSTANDARD = LVCMOS33;
NET sram_a(1) LOC="P142" | IOSTANDARD = LVCMOS33;
NET sram_a(2) LOC="P141" | IOSTANDARD = LVCMOS33;
NET sram_a(3) LOC="P140" | IOSTANDARD = LVCMOS33;
NET sram_a(4) LOC="P139" | IOSTANDARD = LVCMOS33;
NET sram_a(5) LOC="P104" | IOSTANDARD = LVCMOS33;
NET sram_a(6) LOC="P102" | IOSTANDARD = LVCMOS33;
NET sram_a(7) LOC="P101" | IOSTANDARD = LVCMOS33;
NET sram_a(8) LOC="P100" | IOSTANDARD = LVCMOS33;
NET sram_a(9) LOC="P99" | IOSTANDARD = LVCMOS33;
NET sram_a(10) LOC="P112" | IOSTANDARD = LVCMOS33;
NET sram_a(11) LOC="P114" | IOSTANDARD = LVCMOS33;
NET sram_a(12) LOC="P115" | IOSTANDARD = LVCMOS33;
NET sram_a(13) LOC="P116" | IOSTANDARD = LVCMOS33;
NET sram_a(14) LOC="P117" | IOSTANDARD = LVCMOS33;
NET sram_a(15) LOC="P131" | IOSTANDARD = LVCMOS33;
NET sram_a(16) LOC="P133" | IOSTANDARD = LVCMOS33;
NET sram_a(17) LOC="P134" | IOSTANDARD = LVCMOS33;
NET sram_a(18) LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_a<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_a<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET ram_WE_n LOC="P118" | IOSTANDARD=LVCMOS33;
NET ram_d(0) LOC="P132" | IOSTANDARD = LVCMOS33;
NET ram_d(1) LOC="P126" | IOSTANDARD = LVCMOS33;
NET ram_d(2) LOC="P123" | IOSTANDARD = LVCMOS33;
NET ram_d(3) LOC="P120" | IOSTANDARD = LVCMOS33;
NET ram_d(4) LOC="P119" | IOSTANDARD = LVCMOS33;
NET ram_d(5) LOC="P121" | IOSTANDARD = LVCMOS33;
NET ram_d(6) LOC="P124" | IOSTANDARD = LVCMOS33;
NET ram_d(7) LOC="P127" | IOSTANDARD = LVCMOS33;
NET NTSC LOC="P67" | IOSTANDARD=LVCMOS33;
NET PAL LOC="P66" | IOSTANDARD=LVCMOS33;
NET sram_WE_n LOC="P118" | IOSTANDARD = LVCMOS33;
NET "ps2_data" LOC="P97" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "ps2_clk" LOC="P98" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD="TMDS_33";
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD="TMDS_33";
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD="TMDS_33";
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD="TMDS_33";
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD="TMDS_33";
# SD/MMC
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_down" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_left" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_right" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tl" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "j1_tr" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros
NET "hdmi_out_p<0>" LOC="P44" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<0>" LOC="P43" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_p<1>" LOC="P46" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<1>" LOC="P45" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_p<2>" LOC="P48" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<2>" LOC="P47" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_p<3>" LOC="P41" | IOSTANDARD = "TMDS_33";
NET "hdmi_out_n<3>" LOC="P40" | IOSTANDARD = "TMDS_33";

48
cores/MasterSystem/src/sms_zxuno_v4.ucf
View File

@ -29,27 +29,27 @@ NET "ps2_data" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
NET "ram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "ram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "ram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "ram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "ram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "ram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "ram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "ram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "ram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "ram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "ram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "ram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "ram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "ram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "ram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "ram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "ram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "ram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "ram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "ram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "ram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "sram_a<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
NET "sram_a<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
NET "sram_a<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
NET "sram_a<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
NET "sram_a<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
NET "sram_a<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
NET "sram_a<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
NET "sram_a<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
NET "sram_a<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
NET "sram_a<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
NET "sram_a<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
NET "sram_a<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "sram_a<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "sram_a<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
NET "sram_a<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
NET "sram_a<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
NET "sram_a<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
NET "sram_a<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
NET "sram_a<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_a<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_a<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
NET "ram_d<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
NET "ram_d<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
@ -60,7 +60,7 @@ NET "ram_d<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
NET "ram_d<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
NET "ram_d<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
NET "ram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
NET "sram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
@ -71,10 +71,10 @@ NET "ram_WE_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SD/MMC
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "spi_sclk" LOC="P75" | IOSTANDARD = LVCMOS33;
NET "spi_di" LOC="P74" | IOSTANDARD = LVCMOS33;
NET "spi_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
NET "spi_do" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
NET "j1_up" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;

8
cores/SamCoupe/SamCoupe_zxuno_Ap.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# Otros
NET "clk12" PERIOD=83 ns;

8
cores/SamCoupe/SamCoupe_zxuno_v2.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# Otros
NET "clk12" PERIOD=83 ns;

8
cores/SamCoupe/SamCoupe_zxuno_v3.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P118" | IOSTANDARD = LVCMOS33;
# Otros
NET "clk12" PERIOD=83 ns;

8
cores/SamCoupe/SamCoupe_zxuno_v4.ucf
View File

@ -1,5 +1,5 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33;
# Video output
@ -12,8 +12,8 @@ NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
@ -87,5 +87,3 @@ NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# Otros
NET "clk12" PERIOD=83 ns;

39
cores/SamCoupe/asic.v
View File

@ -56,7 +56,8 @@ module asic (
output wire [1:0] g,
output wire [1:0] b,
output wire bright,
output reg csync,
output reg hsync_pal,
output reg vsync_pal,
output wire int_n
);
@ -177,14 +178,17 @@ module asic (
reg rint_n;
always @* begin
csync = 1'b1;
hsync_pal = 1'b1;
vsync_pal = 1'b1;
vint_n = 1'b1;
rint_n = 1'b1;
if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC))
csync = 1'b0;
if (vc >= BEGINVSYNCV && vc < ENDVSYNCV)
csync = ~csync;
if (vc == BEGINVSYNCV && hc < 256)
if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC)) begin
hsync_pal = 1'b0;
end
if (vc >= BEGINVSYNCV && vc < ENDVSYNCV) begin
vsync_pal = 1'b0;
end
if (vc == BEGINVSYNCV && hc < 10'd256)
vint_n = 1'b0;
if (lineint >= 8'd0 && lineint <= 8'd191)
if ({1'b0, lineint} == vc && hc < 10'd256)
@ -197,7 +201,7 @@ module asic (
reg fetching_pixels;
always @* begin
if (vc>=0 && vc<VACTIVEREGION && hc>=256 && hc<HTOTAL)
if (vc>=0 && vc<VACTIVEREGION && hc>=10'd256 && hc<HTOTAL)
fetching_pixels = ~screen_off;
else
fetching_pixels = 1'b0;
@ -226,28 +230,25 @@ module asic (
mem_contention = 1'b0;
io_contention = 1'b0;
// if (screen_off == 1'b0 && hc[3:0]<4'd10)
// io_contention = 1'b1;
// if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
// hc[3:0]==4'd1 ||
// hc[3:0]==4'd8 ||
// hc[3:0]==4'd9) )
// io_contention = 1'b1;
if (screen_off == 1'b0 && hc[3:0]<4'd10)
io_contention = 1'b1;
if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
hc[3:0]==4'd1 ||
hc[3:0]==4'd8 ||
hc[3:0]==4'd9) )
io_contention = 1'b1;
if (fetching_pixels == 1'b1 && hc[3:0]<4'd10) begin
mem_contention = 1'b1;
//io_contention = 1'b1;
end
if (fetching_pixels == 1'b0 && (hc[3:0]==4'd0 ||
hc[3:0]==4'd1 ||
hc[3:0]==4'd8 ||
hc[3:0]==4'd9) ) begin
mem_contention = 1'b1;
//io_contention = 1'b1;
end
if (screen_mode == 2'b00 && hc[3:0]<4'd10 && (hc<10'd128 || hc>=10'd256)) begin
mem_contention = 1'b1; // extra contention for MODE 1
//io_contention = 1'b1;
end
end
assign asic_is_using_ram = mem_contention & fetching_pixels;
@ -465,7 +466,7 @@ module asic (
border <= 8'h00;
end
else begin
if (iorq_n == 1'b0 && wr_n == 1'b0) begin
if (iorq_n == 1'b0 && wr_n == 1'b0 && wait_n == 1'b1) begin
if (cpuaddr[7:0] == IOADDR_BORDER)
border <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_VMPR)

2
cores/SamCoupe/audio_management.v
View File

@ -37,7 +37,7 @@ module dac (DACout, DACin, Clk, Reset);
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
always @(posedge Clk)
begin
if(Reset)
begin

307
cores/SamCoupe/multiboot.v Normal file
View File

@ -0,0 +1,307 @@
module multiboot (
input wire clk_icap, // WARNING: this clock must not be greater than 20MHz (50ns period)
input wire mrst_n
);
reg [4:0] q = 5'b00000;
reg reboot_ff = 1'b0;
always @(posedge clk_icap) begin
q[0] <= ~mrst_n;
q[1] <= q[0];
q[2] <= q[1];
q[3] <= q[2];
q[4] <= q[3];
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
end
multiboot_spartan6 hacer_multiboot (
.CLK(clk_icap),
.MBT_RESET(1'b0),
.MBT_REBOOT(reboot_ff),
.spi_addr(24'h000000)
);
endmodule
module multiboot_spartan6 (
input wire CLK,
input wire MBT_RESET,
input wire MBT_REBOOT,
input wire [23:0] spi_addr
);
reg [15:0] icap_din;
reg icap_ce;
reg icap_wr;
reg [15:0] ff_icap_din_reversed;
reg ff_icap_ce;
reg ff_icap_wr;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
.CE (ff_icap_ce), // Clock enable input
.CLK (CLK), // Clock input
.I (ff_icap_din_reversed), // 16-bit data input
.WRITE (ff_icap_wr) // Write input
);
// -------------------------------------------------
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
// -------------------------------------------------
parameter IDLE = 0,
SYNC_H = 1,
SYNC_L = 2,
CWD_H = 3,
CWD_L = 4,
GEN1_H = 5,
GEN1_L = 6,
GEN2_H = 7,
GEN2_L = 8,
GEN3_H = 9,
GEN3_L = 10,
GEN4_H = 11,
GEN4_L = 12,
GEN5_H = 13,
GEN5_L = 14,
NUL_H = 15,
NUL_L = 16,
MOD_H = 17,
MOD_L = 18,
HCO_H = 19,
HCO_L = 20,
RBT_H = 21,
RBT_L = 22,
NOOP_0 = 23,
NOOP_1 = 24,
NOOP_2 = 25,
NOOP_3 = 26;
reg [4:0] state;
reg [4:0] next_state;
always @*
begin: COMB
case (state)
IDLE:
begin
if (MBT_REBOOT)
begin
next_state = SYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hAA99; // Sync word 1
end
else
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'hFFFF; // Null
end
end
SYNC_H:
begin
next_state = SYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h5566; // Sync word 2
end
SYNC_L:
begin
next_state = NUL_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
NUL_H:
begin
// next_state = NUL_L;
next_state = GEN1_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
end
//Q
GEN1_H:
begin
next_state = GEN1_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
end
GEN1_L:
begin
next_state = GEN2_H;
icap_ce = 0;
icap_wr = 0;
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
end
GEN2_H:
begin
next_state = GEN2_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3281; // Escritura a reg GENERAL_2
end
GEN2_L:
begin
next_state = MOD_H;
icap_ce = 0;
icap_wr = 0;
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
end
/////// Registro MODE (para carga a 4x tras reboot)
MOD_H:
begin
next_state = MOD_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3301; // Escritura a reg MODE
end
MOD_L:
begin
next_state = NUL_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
end
/////
NUL_L:
begin
next_state = RBT_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
RBT_H:
begin
next_state = RBT_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h000E; // REBOOT Command 0x000E
end
//--------------------
RBT_L:
begin
next_state = NOOP_0;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_0:
begin
next_state = NOOP_1;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_1:
begin
next_state = NOOP_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_2:
begin
next_state = NOOP_3;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
//--------------------
NOOP_3:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // NULL value
end
default:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // 16'h1111"
end
endcase
end
always @(posedge CLK)
begin: SEQ
if (MBT_RESET)
state <= IDLE;
else
state <= next_state;
end
always @(posedge CLK)
begin: ICAP_FF
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
ff_icap_din_reversed[1] <= icap_din[6];
ff_icap_din_reversed[2] <= icap_din[5];
ff_icap_din_reversed[3] <= icap_din[4];
ff_icap_din_reversed[4] <= icap_din[3];
ff_icap_din_reversed[5] <= icap_din[2];
ff_icap_din_reversed[6] <= icap_din[1];
ff_icap_din_reversed[7] <= icap_din[0];
ff_icap_din_reversed[8] <= icap_din[15];
ff_icap_din_reversed[9] <= icap_din[14];
ff_icap_din_reversed[10] <= icap_din[13];
ff_icap_din_reversed[11] <= icap_din[12];
ff_icap_din_reversed[12] <= icap_din[11];
ff_icap_din_reversed[13] <= icap_din[10];
ff_icap_din_reversed[14] <= icap_din[9];
ff_icap_din_reversed[15] <= icap_din[8];
ff_icap_ce <= icap_ce;
ff_icap_wr <= icap_wr;
end
endmodule

17
cores/SamCoupe/samcoupe.v
View File

@ -31,7 +31,8 @@ module samcoupe (
output wire [1:0] g,
output wire [1:0] b,
output wire bright,
output wire csync,
output wire hsync_pal,
output wire vsync_pal,
// Audio output
input wire ear,
output wire audio_out_left,
@ -61,6 +62,7 @@ module samcoupe (
wire [7:0] kbcolumns;
wire kb_nmi_n;
wire kb_rst_n;
wire kb_mrst_n;
wire rdmsel;
assign kbrows = {rdmsel, cpuaddr[15:8]};
@ -91,7 +93,7 @@ module samcoupe (
(asic_oe_n == 1'b0)? data_from_asic :
8'hFF;
tv80n el_z80 (
tv80a el_z80 (
.m1_n(),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
@ -148,12 +150,13 @@ module samcoupe (
.g(g),
.b(b),
.bright(bright),
.csync(csync),
.hsync_pal(hsync_pal),
.vsync_pal(vsync_pal),
.int_n(int_n)
);
rom rom_32k (
.clk(clk12),
.clk(clk24),
.a(romaddr),
.dout(data_from_rom)
);
@ -200,7 +203,7 @@ module samcoupe (
.cols(kbcolumns),
.rst_out_n(kb_rst_n),
.nmi_out_n(kb_nmi_n),
.mrst_out_n(),
.mrst_out_n(kb_mrst_n),
.user_toggles(),
//---------------------------------
.zxuno_addr(8'h00),
@ -239,4 +242,8 @@ module samcoupe (
.audio_right(audio_out_right)
);
multiboot back_to_bios (
.clk_icap(clk24), // WARNING: this clock must not be greater than 20MHz (50ns period)
.mrst_n(kb_mrst_n)
);
endmodule

0
cores/SamCoupe/scancode_to_speccy.v → cores/SamCoupe/scancode_to_sam.v
View File

5
cores/SamCoupe/timings.xcf Normal file
View File

@ -0,0 +1,5 @@
#NET "clk50mhz" PERIOD=20 ns;
NET "clk24" KEEP | S | PERIOD=41 ns;
NET "clk12" KEEP | S | PERIOD=82 ns;
NET "clk6" KEEP | S | PERIOD=164 ns;
NET "clk8" KEEP | S | PERIOD=125 ns;

6
cores/SamCoupe/tld_sam.prj
View File

@ -2,15 +2,17 @@ verilog work "tv80_reg.v"
verilog work "tv80_mcode.v"
verilog work "tv80_alu.v"
verilog work "tv80_core.v"
verilog work "scancode_to_speccy.v"
verilog work "scancode_to_sam.v"
verilog work "ps2_port.v"
verilog work "tv80n.v"
verilog work "tv80a.v"
verilog work "saa1099.v"
verilog work "rom.v"
verilog work "ram.v"
verilog work "ps2_keyb.v"
verilog work "multiboot.v"
verilog work "audio_management.v"
verilog work "asic.v"
verilog work "vga_scandoubler.v"
verilog work "samcoupe.v"
verilog work "relojes.v"
verilog work "tld_sam.v"

2
cores/SamCoupe/tld_sam.ut
View File

@ -3,7 +3,7 @@
-g Compress
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:4
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp

56
cores/SamCoupe/tld_sam.v
View File

@ -30,11 +30,12 @@ module tld_sam (
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync,
output wire hsync,
output wire vsync,
output wire stdn,
output wire stdnb,
// SRAM interface
output wire [18:0] sram_addr,
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
// PS/2 keyoard interface
@ -43,24 +44,34 @@ module tld_sam (
);
// Interface with RAM
wire [18:0] ramaddr;
wire [7:0] data_from_ram;
wire [7:0] data_to_ram;
wire ram_we_n;
wire [18:0] sram_addr_from_sam;
wire sram_we_n_from_sam;
// Audio and video
wire [1:0] sam_r, sam_g, sam_b;
wire sam_bright;
assign r = {sam_r, sam_bright};
assign g = {sam_g, sam_bright};
assign b = {sam_b, sam_bright};
// scandoubler
wire hsync_pal, vsync_pal;
wire [2:0] ri = {sam_r, sam_bright};
wire [2:0] gi = {sam_g, sam_bright};
wire [2:0] bi = {sam_b, sam_bright};
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
wire clk24, clk12, clk6, clk8;
reg [7:0] poweron_reset = 8'h00;
reg [1:0] scandoubler_ctrl = 2'b00;
always @(posedge clk6) begin
poweron_reset <= {poweron_reset[6:0], 1'b1};
if (poweron_reset[6] == 1'b0)
scandoubler_ctrl <= sram_data[1:0];
end
assign sram_addr = (poweron_reset[7] == 1'b0)? 21'h008FD5 : {2'b00, sram_addr_from_sam};
assign sram_we_n = (poweron_reset[7] == 1'b0)? 1'b1 : sram_we_n_from_sam;
relojes los_relojes (
.CLK_IN1 (clk50mhz), // IN
// Clock out ports
@ -75,13 +86,14 @@ module tld_sam (
.clk12(clk12),
.clk6(clk6),
.clk8(clk8),
.master_reset_n(1'b1), // esta señal es sólo para simulación
.master_reset_n(poweron_reset[7]),
// Video output
.r(sam_r),
.g(sam_g),
.b(sam_b),
.bright(sam_bright),
.csync(csync),
.hsync_pal(hsync_pal),
.vsync_pal(vsync_pal),
// Audio output
.ear(~ear),
.audio_out_left(audio_out_left),
@ -90,8 +102,26 @@ module tld_sam (
.clkps2(clkps2),
.dataps2(dataps2),
// SRAM external interface
.sram_addr(sram_addr),
.sram_addr(sram_addr_from_sam),
.sram_data(sram_data),
.sram_we_n(sram_we_n)
.sram_we_n(sram_we_n_from_sam)
);
vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
.clkvideo(clk12),
.clkvga(clk24),
.enable_scandoubling(scandoubler_ctrl[0]),
.disable_scaneffect(~scandoubler_ctrl[1]),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
endmodule

8
cores/SamCoupe/tld_sam.xst
View File

@ -2,20 +2,22 @@ set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn tld_sam.prj
-infer_ramb8 No
-ofn tld_sam
-ofmt NGC
-p xc6slx9-2-tqg144
-top tld_sam
-opt_mode Speed
-opt_level 1
-opt_level 2
-power NO
-uc "timings.xcf"
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-write_timing_constraints YES
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
@ -35,7 +37,7 @@ run
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto

106
cores/SamCoupe/tv80n.v → cores/SamCoupe/tv80a.v
View File

@ -25,7 +25,7 @@
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
module tv80n (/*AUTOARG*/
module tv80a (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
@ -33,7 +33,7 @@ module tv80n (/*AUTOARG*/
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter T2Write = 1; // 1 => wr_n active in T3, 0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
@ -59,10 +59,6 @@ module tv80n (/*AUTOARG*/
reg iorq_n;
reg rd_n;
reg wr_n;
reg nxt_mreq_n;
reg nxt_iorq_n;
reg nxt_rd_n;
reg nxt_wr_n;
wire cen;
wire intcycle_n;
@ -102,56 +98,71 @@ module tv80n (/*AUTOARG*/
.intcycle_n (intcycle_n)
);
reg [6:0] tstate_r = 7'h00;
reg [6:0] tstate_rr = 7'h00;
always @(negedge clk) begin
tstate_r <= tstate;
end
always @(posedge clk) begin
tstate_rr <= tstate;
end
wire mreq_read = ~iorq & ~no_read & ~write;
wire mreq_write = ~iorq & ~no_read & write;
wire iorq_read = iorq & ~no_read & ~write;
wire iorq_write = iorq & ~no_read & write;
always @* begin
nxt_mreq_n = 1;
nxt_rd_n = 1;
nxt_iorq_n = 1;
nxt_wr_n = 1;
mreq_n = 1;
rd_n = 1;
iorq_n = 1;
wr_n = 1;
if (mcycle[0]) begin
if (tstate[1] || tstate[2]) begin
nxt_rd_n = ~ intcycle_n;
nxt_mreq_n = ~ intcycle_n;
nxt_iorq_n = intcycle_n;
end
end // if (mcycle[0])
else begin
if ((tstate[1] || tstate[2]) && !no_read && !write) begin
nxt_rd_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
end
if (T2Write == 0) begin
if (tstate[2] && write) begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
if (intcycle_n == 1'b1) begin
if (tstate_r[1] || tstate[2]) begin
mreq_n = 1'b0;
rd_n = 1'b0;
end
else if (rfsh_n == 1'b0 && tstate_r[3]) begin
mreq_n = 1'b0;
end
end
else begin
if ((tstate[1] || (tstate[2] && !wait_n)) && write) begin
nxt_wr_n = 1'b0;
nxt_iorq_n = ~ iorq;
nxt_mreq_n = iorq;
if (tstate[2]) begin
iorq_n = 1'b0;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
end // always @ *
always @(negedge clk) begin
if (!reset_n) begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
end
end
else begin
rd_n <= #1 nxt_rd_n;
wr_n <= #1 nxt_wr_n;
iorq_n <= #1 nxt_iorq_n;
mreq_n <= #1 nxt_mreq_n;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
if (mreq_read == 1'b1) begin
if (tstate_r[1] || tstate_r[2]) begin
mreq_n = 1'b0;
rd_n = 1'b0;
end
end
else if (mreq_write == 1'b1) begin
if (tstate_r[1] || tstate_r[2]) begin
mreq_n = 1'b0;
if (tstate_r[2]) begin
wr_n = 1'b0;
end
end
end
else if (iorq_read == 1'b1) begin
if (tstate_rr[1] || tstate_r[2]) begin
iorq_n = 1'b0;
rd_n = 1'b0;
end
end
else if (iorq_write == 1'b1) begin
if (tstate_rr[1] || tstate_r[2]) begin
iorq_n = 1'b0;
wr_n = 1'b0;
end
end
end
end
always @(posedge clk) begin
if (!reset_n) begin
@ -164,4 +175,3 @@ module tv80n (/*AUTOARG*/
end // always @ (posedge clk)
endmodule // t80n

207
cores/SamCoupe/vga_scandoubler.v Normal file
View File

@ -0,0 +1,207 @@
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:57:54 11/09/2015
// Design Name:
// Module Name: vga_scandoubler
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_scandoubler (
input wire clkvideo,
input wire clkvga,
input wire enable_scandoubling,
input wire disable_scaneffect, // 1 to disable scanlines
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
input wire hsync_ext_n,
input wire vsync_ext_n,
output reg [2:0] ro,
output reg [2:0] go,
output reg [2:0] bo,
output reg hsync,
output reg vsync
);
parameter [31:0] CLKVIDEO = 12000;
// http://www.epanorama.net/faq/vga2rgb/calc.html
// SVGA 800x600
// HSYNC = 3.36us VSYNC = 114.32us
parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000;
parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000;
reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000;
reg [9:0] totalhor = 10'd0;
wire [2:0] rout, gout, bout;
// Memoria de doble puerto que guarda la información de dos scans
// Cada scan puede ser de hasta 1024 puntos, incluidos aquí los
// puntos en negro que se pintan durante el HBlank
vgascanline_dport memscan (
.clk(clkvga),
.addrwrite(addrvideo),
.addrread(addrvga),
.we(1'b1),
.din({ri,gi,bi}),
.dout({rout,gout,bout})
);
// Para generar scanlines:
reg scaneffect = 1'b0;
wire [2:0] rout_dimmed, gout_dimmed, bout_dimmed;
color_dimmed apply_to_red (rout, rout_dimmed);
color_dimmed apply_to_green (gout, gout_dimmed);
color_dimmed apply_to_blue (bout, bout_dimmed);
wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : rout_dimmed;
wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : gout_dimmed;
wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : bout_dimmed;
// Voy alternativamente escribiendo en una mitad o en otra del scan buffer
// Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal
// En "totalhor" mido el número de ciclos de reloj que hay en un scan
always @(posedge clkvideo) begin
// if (vsync_ext_n == 1'b0) begin
// addrvideo <= 11'd0;
// end
if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin
totalhor <= addrvideo[9:0];
addrvideo <= {~addrvideo[10],10'b0000000000};
end
else
addrvideo <= addrvideo + 11'd1;
end
// Recorro el scanbuffer al doble de velocidad, generando direcciones para
// el scan buffer. Cada vez que el video original ha terminado una linea,
// cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no
// estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer
// desde el mismo origen
// Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que
// uso después para mostrar los píxeles a su brillo nominal, o con su brillo
// reducido para un efecto chachi de scanlines en la VGA
always @(posedge clkvga) begin
// if (vsync_ext_n == 1'b0) begin
// addrvga <= 11'b10000000000;
// scaneffect <= 1'b0;
// end
if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin
addrvga <= {addrvga[10], 10'b000000000};
scaneffect <= ~scaneffect;
end
else if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin
addrvga <= {~addrvga[10],10'b000000000};
scaneffect <= ~scaneffect;
end
else
addrvga <= addrvga + 11'd1;
end
// El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo
// del barrido de un scanline
reg hsync_vga, vsync_vga;
always @* begin
if (addrvga[9:0] < HSYNC_COUNT[9:0])
hsync_vga = 1'b0;
else
hsync_vga = 1'b1;
end
// El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de
// bajada de la señal de sincronismo vertical original
reg [15:0] cntvsync = 16'hFFFF;
initial vsync_vga = 1'b1;
always @(posedge clkvga) begin
if (vsync_ext_n == 1'b0) begin
if (cntvsync == 16'hFFFF) begin
cntvsync <= 16'd0;
vsync_vga <= 1'b0;
end
else if (cntvsync != 16'hFFFE) begin
if (cntvsync == VSYNC_COUNT[15:0]) begin
vsync_vga <= 1'b1;
cntvsync <= 16'hFFFE;
end
else
cntvsync <= cntvsync + 16'd1;
end
end
else if (vsync_ext_n == 1'b1)
cntvsync <= 16'hFFFF;
end
always @* begin
if (enable_scandoubling == 1'b0) begin // 15kHz output
ro = ri;
go = gi;
bo = bi;
hsync = hsync_ext_n ^ ~vsync_ext_n;
vsync = 1'b1;
end
else begin // VGA output
ro = ro_vga;
go = go_vga;
bo = bo_vga;
hsync = hsync_vga;
vsync = vsync_vga;
end
end
endmodule
// Una memoria de doble puerto: uno para leer, y otro para
// escribir. Es de 2048 direcciones: 1024 se emplean para
// guardar un scan, y otros 1024 para el siguiente scan
module vgascanline_dport (
input wire clk,
input wire [10:0] addrwrite,
input wire [10:0] addrread,
input wire we,
input wire [8:0] din,
output reg [8:0] dout
);
reg [8:0] scan[0:2047]; // two scanlines
always @(posedge clk) begin
dout <= scan[addrread];
if (we == 1'b1)
scan[addrwrite] <= din;
end
endmodule
module color_dimmed (
input wire [2:0] in,
output reg [2:0] out // out is scaled to roughly 70% of in
);
always @* begin // a LUT
case (in)
3'd0 : out = 3'd0;
3'd1 : out = 3'd1;
3'd2 : out = 3'd1;
3'd3 : out = 3'd2;
3'd4 : out = 3'd3;
3'd5 : out = 3'd3;
3'd6 : out = 3'd4;
3'd7 : out = 3'd5;
default: out = 3'd0;
endcase
end
endmodule