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Actualizo a zxpp02

This commit is contained in:
antoniovillena 2016-08-23 21:30:41 +02:00
parent c2b3846598
commit ba5db596ff
3 changed files with 84 additions and 6 deletions
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3
cores/KypSpectrum/loram.ngc Normal file
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File diff suppressed because one or more lines are too long

47
cores/KypSpectrum/vga.vhd
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@ -15,6 +15,8 @@ entity vga is
port
(
clock25 : in std_logic;
va : out std_logic_vector(12 downto 0);
vd : in std_logic_vector( 7 downto 0);
hs : out std_logic;
vs : out std_logic;
rgb : out std_logic_vector(11 downto 0)
@ -23,12 +25,23 @@ end;
architecture behavioral of vga is
signal x : std_logic_vector(9 downto 0);
signal y : std_logic_vector(9 downto 0);
signal x : std_logic_vector( 9 downto 0);
signal y : std_logic_vector( 9 downto 0);
signal f : std_logic_vector( 5 downto 0);
signal xy : std_logic_vector(17 downto 0);
signal bmap : std_logic_vector( 7 downto 0);
signal attr : std_logic_vector( 7 downto 0);
type tpalette is array (0 to 15) of std_logic_vector(11 downto 0);
constant palette : tpalette := ( x"000", x"007", x"700", x"707", x"070", x"077", x"770", x"777", x"000", x"00f", x"f00", x"f0f", x"0f0", x"0ff", x"ff0", x"fff" );
begin
process(clock25)
variable bpre : std_logic_vector(7 downto 0);
variable apre : std_logic_vector(7 downto 0);
variable i, p : std_logic_vector(2 downto 0);
variable b, c : integer;
begin
if rising_edge(clock25) then
if x < 799 then x <= x+1;
@ -37,14 +50,40 @@ begin
if y < 524 then y <= y+1;
else
y <= (others => '0');
f <= f+1;
end if;
end if;
if x >= 640+16 and x < 640+16+96 then hs <= '0'; else hs <= '1'; end if;
if y >= 480+10 and y < 480+10+ 2 then vs <= '0'; else vs <= '1'; end if;
if x < 640 and y < 480 then
rgb <= x"777";
if x >= 64 and x < 64+512 and y >= 48 and y < 48+384 then
if x = 64+512-16 and y = 48+383 then xy <= (others => '0'); else xy <= xy+1; end if;
if xy(3 downto 0) = "0000" then va <= xy(17 downto 16)&xy(12 downto 10)&xy(15 downto 13)&xy(8 downto 4); end if;
if xy(3 downto 0) = "1000" then va <= "110"&xy(17 downto 13)&xy( 8 downto 4); end if;
if xy(3 downto 0) = "0010" then bpre := vd; end if;
if xy(3 downto 0) = "1010" then apre := vd; end if;
if xy(3 downto 0) = "1110" then bmap <= bpre; attr <= apre; end if;
b := 7-to_integer(unsigned(x(3 downto 1)));
i := attr(2 downto 0);
p := attr(5 downto 3);
if attr(7) = '1' then
if f(5) = '1' then
if bmap(b) = '0' then c := to_integer(unsigned(i)); else c := to_integer(unsigned(p)); end if;
else
if bmap(b) = '0' then c := to_integer(unsigned(p)); else c := to_integer(unsigned(i)); end if;
end if;
else
if bmap(b) = '1' then c := to_integer(unsigned(i)); else c := to_integer(unsigned(p)); end if;
end if;
if attr(6) = '1' then c := c+8; end if;
rgb <= palette(c);
elsif x < 640 and y < 480 then
rgb <= x"700";
else
rgb <= x"000";
end if;

40
cores/KypSpectrum/zxpp.vhd
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@ -24,18 +24,38 @@ architecture structural of zxpp is
);
end component;
component loram
port
(
clka : in std_logic;
wea : in std_logic_vector( 0 downto 0);
addra : in std_logic_vector(13 downto 0);
dina : in std_logic_vector( 7 downto 0);
douta : out std_logic_vector( 7 downto 0);
clkb : in std_logic;
web : in std_logic_vector( 0 downto 0);
addrb : in std_logic_vector(13 downto 0);
dinb : in std_logic_vector( 7 downto 0);
doutb : out std_logic_vector( 7 downto 0)
);
end component;
component vga is
port
(
clock25 : in std_logic;
va : out std_logic_vector(12 downto 0);
vd : in std_logic_vector( 7 downto 0);
hs : out std_logic;
vs : out std_logic;
rgb : out std_logic_vector(11 downto 0)
);
end component;
signal clock25 : std_logic;
signal clock14 : std_logic;
signal clock25 : std_logic;
signal clock14 : std_logic;
signal va : std_logic_vector(12 downto 0);
signal vd : std_logic_vector( 7 downto 0);
begin
@ -45,9 +65,25 @@ begin
clock25 => clock25,
clock14 => clock14
);
Uloram: loram port map
(
clka => '0',
wea(0) => '0',
addra => (others => '0'),
dina => (others => '0'),
douta => open,
clkb => clock25,
web(0) => '0',
addrb(13) => '0',
addrb(12 downto 0) => va,
dinb => (others => '0'),
doutb => vd
);
Uvga: vga port map
(
clock25 => clock25,
va => va,
vd => vd,
hs => netHS,
vs => netVS,
rgb(11 downto 8) => netR,