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Actualizo core y firmware a última versión

This commit is contained in:
antoniovillena 2016-05-20 15:11:57 +02:00
parent d2f5e7ccc0
commit bf4fe68698
20 changed files with 7688 additions and 729 deletions
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16
cores/Spectrum/audio_management.v
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@ -77,19 +77,15 @@ module mixer (
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255; ({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
reg [7:0] mezcla; reg [7:0] mezcla;
reg [3:0] cntsamples = 4'd0;
reg [1:0] sndsource = 2'd0; reg [1:0] sndsource = 2'd0;
always @(posedge clkdac) begin always @(posedge clkdac) begin
if (cntsamples == 4'd0) begin // cada 256 cuentas de reloj, cambiamos de fuente de sonido case (sndsource)
case (sndsource) SRC_BEEPER: mezcla <= beeper;
SRC_BEEPER: mezcla <= beeper; SRC_AY1 : mezcla <= ay1;
SRC_AY1 : mezcla <= ay1; SRC_AY2 : mezcla <= ay2;
SRC_AY2 : mezcla <= ay2; endcase
endcase sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
end
cntsamples <= cntsamples + 4'd1;
end end
dac audio_dac ( dac audio_dac (

42
cores/Spectrum/bootloader_hex.txt
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@ -1,5 +1,5 @@
31 31
B1 AE
BF BF
11 11
61 61
@ -10,7 +10,7 @@ D5
ED ED
D5 D5
01 01
AE AB
BF BF
18 18
2B 2B
@ -49,11 +49,11 @@ FE
ED ED
A3 A3
E9 E9
5A 05
58 ED
55 61
6E 04
6F C9
C3 C3
43 43
C0 C0
@ -67,15 +67,18 @@ EF
08 08
DB DB
1F 1F
F6 E6
E7 1F
3C FE
28 18
28 28
27
EF
0B
80
EF EF
03 03
01 01
AF
EF EF
03 03
00 00
@ -83,23 +86,20 @@ EF
02 02
03 03
ED ED
79 61
39
ED ED
59 59
ED ED
79 61
39
ED ED
A2 A2
04 04
BC BC
38 38
FA FA
05 18
ED CD
61
04
C9
C3 C3
40 40
C0 C0
@ -128,7 +128,7 @@ C0
02 02
40 40
2E 2E
62 34
E5 E5
3E 3E
0F 0F

2
cores/Spectrum/control_enable_options.v
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@ -1,4 +1,6 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
// Company: // Company:
// Engineer: // Engineer:

4
cores/Spectrum/coreid.v
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@ -39,8 +39,8 @@ module coreid (
text[ 1] = "2"; text[ 1] = "2";
text[ 2] = "1"; text[ 2] = "1";
text[ 3] = "-"; text[ 3] = "-";
text[ 4] = "0"; text[ 4] = "1";
text[ 5] = "5"; text[ 5] = "7";
text[ 6] = "0"; text[ 6] = "0";
text[ 7] = "5"; text[ 7] = "5";
text[ 8] = "2"; text[ 8] = "2";

94
cores/Spectrum/cuatro_relojes.v
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@ -16,10 +16,16 @@ module clock_generator
output wire CLK_OUT4, output wire CLK_OUT4,
output wire cpuclk output wire cpuclk
); );
wire clkin1_buffered;
IBUFG BUFG_IN (
.O(clkin1_buffered),
.I(CLK_IN1)
);
reg [2:0] pll_option_stored = 3'b000; reg [2:0] pll_option_stored = 3'b000;
reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot
always @(posedge CLK_IN1) begin always @(posedge clkin1_buffered) begin
if (pll_option != pll_option_stored) begin if (pll_option != pll_option_stored) begin
pll_option_stored <= pll_option; pll_option_stored <= pll_option;
pulso_reconf <= 8'b00000001; pulso_reconf <= 8'b00000001;
@ -42,7 +48,7 @@ module clock_generator
.RST(1'b0), .RST(1'b0),
// CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the // CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the
// clock for the PLL_DRP module // clock for the PLL_DRP module
.CLKIN(CLK_IN1), .CLKIN(clkin1_buffered),
// SRDY pulses for one clock cycle after the PLL_ADV is locked and the // SRDY pulses for one clock cycle after the PLL_ADV is locked and the
// PLL_DRP module is ready to start another re-configuration // PLL_DRP module is ready to start another re-configuration
.SRDY(), .SRDY(),
@ -54,58 +60,6 @@ module clock_generator
.CLK3OUT(CLK_OUT4) .CLK3OUT(CLK_OUT4)
); );
// wire clk28, clk14, clk7, clk3d5, cpuclk_3_2, cpuclk_1_0;
//
// BUFGMUX reloj28_contenido (
// .O(clk28),
// .I0(CLK_OUT1),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX reloj14_contenido (
// .O(clk14),
// .I0(CLK_OUT2),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX reloj7_contenido (
// .O(clk7),
// .I0(CLK_OUT3),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX reloj3d5_contenido (
// .O(clk3d5),
// .I0(CLK_OUT4),
// .I1(1'b1),
// .S(CPUContention)
// );
//
// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
// .O(cpuclk_3_2),
// .I0(clk14),
// .I1(clk28),
// .S(turbo_enable[0])
// );
//
// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
// .O(cpuclk_1_0),
// .I0(clk3d5),
// .I1(clk7),
// .S(turbo_enable[0])
// );
//
// BUFGMUX cpuclk_selector (
// .O(cpuclk),
// .I0(cpuclk_1_0),
// .I1(cpuclk_3_2),
// .S(turbo_enable[1])
// );
wire cpuclk_selected, cpuclk_3_2, cpuclk_1_0; wire cpuclk_selected, cpuclk_3_2, cpuclk_1_0;
// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU // BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU
@ -115,17 +69,43 @@ module clock_generator
// .S(turbo_enable[0]) // .S(turbo_enable[0])
// ); // );
// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
// .O(cpuclk_1_0),
// .I0(CLK_OUT4),
// .I1(CLK_OUT3),
// .S(turbo_enable[0])
// );
//
// BUFGMUX cpuclk_selector (
// .O(cpuclk_selected),
// .I0(cpuclk_1_0),
// .I1(CLK_OUT2),
// .S(turbo_enable[1])
// );
//
// BUFGMUX aplicar_contienda (
// .O(cpuclk),
// .I0(cpuclk_selected), // when no contention, clock is this one
// .I1(1'b1), // during contention, clock is pulled up
// .S(CPUContention) // contention signal
// );
reg [2:0] clkdivider = 3'b000;
always @(posedge CLK_OUT1)
clkdivider <= clkdivider + 3'd1;
BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU
.O(cpuclk_1_0), .O(cpuclk_1_0),
.I0(CLK_OUT4), .I0(clkdivider[2]),
.I1(CLK_OUT3), .I1(clkdivider[1]),
.S(turbo_enable[0]) .S(turbo_enable[0])
); );
BUFGMUX cpuclk_selector ( BUFGMUX cpuclk_selector (
.O(cpuclk_selected), .O(cpuclk_selected),
.I0(cpuclk_1_0), .I0(cpuclk_1_0),
.I1(CLK_OUT2), .I1(clkdivider[0]),
.S(turbo_enable[1]) .S(turbo_enable[1])
); );

6912
cores/Spectrum/initial_bootscreen.hex Normal file
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File diff suppressed because it is too large Load Diff

34
cores/Spectrum/new_memory.v
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@ -1,4 +1,6 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
// Company: // Company:
// Engineer: // Engineer:
@ -163,9 +165,9 @@ module new_memory (
end end
end end
`define ADDR_7FFD_PLUS2A (a[0] && !a[1] && a[14] && !a[15]) // TO-DO repasar esta codificacion!!!! `define ADDR_7FFD_PLUS2A (!a[1] && a[15:14]==2'b01)
`define ADDR_7FFD_SP128 (a[0] && !a[1] && !a[15]) `define ADDR_7FFD_SP128 (!a[1] && !a[15])
`define ADDR_1FFD (a[0] && !a[1] && a[12] && a[15:13]==3'b000) `define ADDR_1FFD (!a[1] && a[15:12]==4'b0001)
`define ADDR_TIMEX_MMU (a[7:0] == 8'hF4) `define ADDR_TIMEX_MMU (a[7:0] == 8'hF4)
`define PAGE0 3'b000 `define PAGE0 3'b000
@ -184,7 +186,7 @@ module new_memory (
wire puerto_bloqueado = bank128[5]; wire puerto_bloqueado = bank128[5];
wire [2:0] banco_ram = bank128[2:0]; wire [2:0] banco_ram = bank128[2:0];
wire vrampage = bank128[3]; wire vrampage = bank128[3];
wire [1:0] banco_rom = {bankplus3[2] & ~disable_romsel1f, bank128[4] & ~disable_romsel7f}; wire [1:0] banco_rom = {bankplus3[2] & (~disable_romsel1f), bank128[4] & (~disable_romsel7f)};
wire amstrad_allram_page_mode = bankplus3[0]; wire amstrad_allram_page_mode = bankplus3[0];
wire [1:0] plus3_memory_arrangement = bankplus3[2:1]; wire [1:0] plus3_memory_arrangement = bankplus3[2:1];
@ -194,14 +196,18 @@ module new_memory (
bankplus3 <= 8'h00; bankplus3 <= 8'h00;
timex_mmu <= 8'h00; timex_mmu <= 8'h00;
end end
else if (!disable_1ffd && !iorq_n && !wr_n && `ADDR_1FFD && !puerto_bloqueado) else begin
bankplus3 <= din; if (!disable_1ffd && !disable_7ffd) begin
else if (!disable_7ffd && disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_SP128 && !puerto_bloqueado) if (!iorq_n && !wr_n && `ADDR_1FFD && !puerto_bloqueado)
bank128 <= din; bankplus3 <= din;
else if (!disable_7ffd && !disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_PLUS2A && !puerto_bloqueado) if (!iorq_n && !wr_n && `ADDR_7FFD_PLUS2A && !puerto_bloqueado)
bank128 <= din; bank128 <= din;
else if (enable_timexmmu && !iorq_n && !wr_n && `ADDR_TIMEX_MMU) end
timex_mmu <= din; if (!disable_7ffd && disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_SP128 && !puerto_bloqueado)
bank128 <= din;
if (enable_timexmmu && !iorq_n && !wr_n && `ADDR_TIMEX_MMU)
timex_mmu <= din;
end
end end
reg [18:0] addr_port2; reg [18:0] addr_port2;
@ -444,7 +450,7 @@ module new_memory (
endmodule endmodule
module sram_and_mirror ( module sram_and_mirror (
input wire clk, // 28MHz or higher if possible input wire clk, // 28MHz
input wire [14:0] a1, // to BRAM addr bus input wire [14:0] a1, // to BRAM addr bus
input wire [18:0] a2, // to SRAM addr bus input wire [18:0] a2, // to SRAM addr bus
input wire we2_n, // to SRAM WE enable input wire we2_n, // to SRAM WE enable
@ -478,6 +484,6 @@ module sram_and_mirror (
assign a = a2; assign a = a2;
assign we_n = we2_n; assign we_n = we2_n;
assign dout2 = d; assign dout2 = d;
assign d = (we2_n == 1'b0)? din2 : 8'hZZ; assign d = (we_n == 1'b0)? din2 : 8'hZZ;
endmodule endmodule

1122
cores/Spectrum/pll_drp.v
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File diff suppressed because it is too large Load Diff

9
cores/Spectrum/pll_top.v
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@ -79,8 +79,6 @@ module pll_top
wire locked; wire locked;
// These signals are used for the BUFG's necessary for the design. // These signals are used for the BUFG's necessary for the design.
wire clkin_bufgout;
wire clkfb_bufgout; wire clkfb_bufgout;
wire clkfb_bufgin; wire clkfb_bufgin;
@ -103,11 +101,6 @@ module pll_top
wire clk5_bufgout; wire clk5_bufgout;
// Global buffers used in design // Global buffers used in design
// BUFG BUFG_IN (
// .O(clkin_bufgout),
// .I(CLKIN)
// );
assign clkin_bufgout = CLKIN;
BUFG BUFG_FB ( BUFG BUFG_FB (
.O(clkfb_bufgout), .O(clkfb_bufgout),
@ -337,7 +330,7 @@ module pll_top
.SRDY(SRDY), .SRDY(SRDY),
// Input from IBUFG // Input from IBUFG
.SCLK(clkin_bufgout), .SCLK(CLKIN),
// Direct connections to the PLL_ADV // Direct connections to the PLL_ADV
.DO(dout), .DO(dout),

4
cores/Spectrum/rom.v
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@ -24,7 +24,7 @@ module rom (
output reg [7:0] dout output reg [7:0] dout
); );
reg [7:0] mem[0:255]; reg [7:0] mem[0:255]; //127
integer i; integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
for (i=0;i<256;i=i+1) begin for (i=0;i<256;i=i+1) begin
@ -34,6 +34,6 @@ module rom (
end end
always @(posedge clk) begin always @(posedge clk) begin
dout <= mem[a[7:0]]; dout <= mem[a[7:0]]; //6:0
end end
endmodule endmodule

110
cores/Spectrum/zxuno.v
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@ -65,7 +65,7 @@ module zxuno (
input wire joyleft, input wire joyleft,
input wire joyright, input wire joyright,
input wire joyfire, input wire joyfire,
// MOUSE // MOUSE
inout wire mouseclk, inout wire mouseclk,
inout wire mousedata, inout wire mousedata,
@ -81,7 +81,7 @@ module zxuno (
wire mreq_n,iorq_n,rd_n,wr_n,int_n,m1_n,nmi_n,rfsh_n; wire mreq_n,iorq_n,rd_n,wr_n,int_n,m1_n,nmi_n,rfsh_n;
wire enable_nmi_n; wire enable_nmi_n;
wire [15:0] cpuaddr; wire [15:0] cpuaddr;
wire [7:0] cpudin; reg [7:0] cpudin;
wire [7:0] cpudout; wire [7:0] cpudout;
wire [7:0] ula_dout; wire [7:0] ula_dout;
@ -191,24 +191,46 @@ module zxuno (
// Asignación de dato para la CPU segun la decodificación de todos los dispositivos // Asignación de dato para la CPU segun la decodificación de todos los dispositivos
// conectados a ella. // conectados a ella.
assign cpudin = (oe_n_romyram==1'b0)? memory_dout : // assign cpudin = (oe_n_romyram==1'b0)? memory_dout :
(oe_n_ay==1'b0)? ay_dout : // (oe_n_ay==1'b0)? ay_dout :
(oe_n_joystick==1'b0)? joystick_dout : // (oe_n_joystick==1'b0)? joystick_dout :
(oe_n_zxunoaddr==1'b0)? zxuno_addr_to_cpu : // (oe_n_zxunoaddr==1'b0)? zxuno_addr_to_cpu :
(oe_n_spi==1'b0)? spi_dout : // (oe_n_spi==1'b0)? spi_dout :
(oe_n_scancode==1'b0)? scancode_dout : // (oe_n_scancode==1'b0)? scancode_dout :
(oe_n_kbstatus==1'b0)? kbstatus_dout : // (oe_n_kbstatus==1'b0)? kbstatus_dout :
(oe_n_coreid==1'b0)? coreid_dout : // (oe_n_coreid==1'b0)? coreid_dout :
(oe_n_keymap==1'b0)? keymap_dout : // (oe_n_keymap==1'b0)? keymap_dout :
(oe_n_scratch==1'b0)? scratch_dout : // (oe_n_scratch==1'b0)? scratch_dout :
(oe_n_scndblctrl==1'b0)? scndblctrl_dout : // (oe_n_scndblctrl==1'b0)? scndblctrl_dout :
(oe_n_nmievents==1'b0)? nmievents_dout : // (oe_n_nmievents==1'b0)? nmievents_dout :
(oe_n_kmouse==1'b0)? kmouse_dout : // (oe_n_kmouse==1'b0)? kmouse_dout :
(oe_n_mousedata==1'b0)? mousedata_dout : // (oe_n_mousedata==1'b0)? mousedata_dout :
(oe_n_mousestatus==1'b0)? mousestatus_dout : // (oe_n_mousestatus==1'b0)? mousestatus_dout :
(oe_n_rasterint==1'b0)? rasterint_dout : // (oe_n_rasterint==1'b0)? rasterint_dout :
(oe_n_devoptions==1'b0)? devoptions_dout : // (oe_n_devoptions==1'b0)? devoptions_dout :
ula_dout; // ula_dout;
always @* begin
case (1'b0)
oe_n_ay : cpudin = ay_dout;
oe_n_joystick : cpudin = joystick_dout;
oe_n_zxunoaddr : cpudin = zxuno_addr_to_cpu;
oe_n_spi : cpudin = spi_dout;
oe_n_scancode : cpudin = scancode_dout;
oe_n_kbstatus : cpudin = kbstatus_dout;
oe_n_coreid : cpudin = coreid_dout;
oe_n_keymap : cpudin = keymap_dout;
oe_n_scratch : cpudin = scratch_dout;
oe_n_scndblctrl : cpudin = scndblctrl_dout;
oe_n_nmievents : cpudin = nmievents_dout;
oe_n_kmouse : cpudin = kmouse_dout;
oe_n_mousedata : cpudin = mousedata_dout;
oe_n_mousestatus : cpudin = mousestatus_dout;
oe_n_rasterint : cpudin = rasterint_dout;
oe_n_devoptions : cpudin = devoptions_dout;
oe_n_romyram : cpudin = memory_dout;
default : cpudin = ula_dout;
endcase
end
tv80n_wrapper el_z80 ( tv80n_wrapper el_z80 (
.m1_n(m1_n), .m1_n(m1_n),
@ -232,7 +254,7 @@ module zxuno (
); );
ula_radas la_ula ( ula_radas la_ula (
// Clocks // Clocks
.clk14(clk14), // 14MHz master clock .clk14(clk14), // 14MHz master clock
.clk7(clk7), .clk7(clk7),
.wssclk(wssclk), // 5MHz WSS clock .wssclk(wssclk), // 5MHz WSS clock
@ -240,15 +262,15 @@ module zxuno (
.CPUContention(CPUContention), .CPUContention(CPUContention),
.rst_n(mrst_n & rst_n & power_on_reset_n), .rst_n(mrst_n & rst_n & power_on_reset_n),
// CPU interface // CPU interface
.a(cpuaddr), .a(cpuaddr),
.access_to_contmem(access_to_screen), .access_to_contmem(access_to_screen),
.mreq_n(mreq_n), .mreq_n(mreq_n),
.iorq_n(iorq_n), .iorq_n(iorq_n),
.rd_n(rd_n), .rd_n(rd_n),
.wr_n(wr_n), .wr_n(wr_n),
.int_n(int_n), .int_n(int_n),
.din(cpudout), .din(cpudout),
.dout(ula_dout), .dout(ula_dout),
.rasterint_enable(rasterint_enable), .rasterint_enable(rasterint_enable),
.vretraceint_disable(vretraceint_disable), .vretraceint_disable(vretraceint_disable),
@ -258,7 +280,7 @@ module zxuno (
// VRAM interface // VRAM interface
.va(vram_addr), // 16KB videoram, 2 pages .va(vram_addr), // 16KB videoram, 2 pages
.vramdata(vram_dout), .vramdata(vram_dout),
// I/O ports // I/O ports
.ear(ear), .ear(ear),
.mic(mic), .mic(mic),
@ -271,10 +293,10 @@ module zxuno (
.enable_timexmmu(enable_timexmmu), .enable_timexmmu(enable_timexmmu),
// Video // Video
.r(r), .r(r),
.g(g), .g(g),
.b(b), .b(b),
.hsync(hsync), .hsync(hsync),
.vsync(vsync) .vsync(vsync)
); );
@ -533,7 +555,7 @@ module zxuno (
multiboot el_multiboot ( multiboot el_multiboot (
.clk(clk), .clk(clk),
.clk_icap(clk), .clk_icap(clk14),
.rst_n(rst_n & mrst_n & power_on_reset_n), .rst_n(rst_n & mrst_n & power_on_reset_n),
.kb_boot_core(boot_second_core), .kb_boot_core(boot_second_core),
.zxuno_addr(zxuno_addr), .zxuno_addr(zxuno_addr),
@ -567,21 +589,21 @@ module zxuno (
.oe_n(oe_n_ay), .oe_n(oe_n_ay),
.audio_out_ay1(ay1_audio), .audio_out_ay1(ay1_audio),
.audio_out_ay2(ay2_audio) .audio_out_ay2(ay2_audio)
); );
/////////////////////////////////// ///////////////////////////////////
// SOUND MIXER // SOUND MIXER
/////////////////////////////////// ///////////////////////////////////
// 8-bit mixer to generate different audio levels according to input sources // 8-bit mixer to generate different audio levels according to input sources
mixer audio_mix( mixer audio_mix(
.clkdac(clk), .clkdac(clk),
.reset(1'b0), .reset(1'b0),
.mic(mic), .mic(mic),
.spk(spk), .spk(spk),
.ear(ear), .ear(ear),
.ay1(ay1_audio), .ay1(ay1_audio),
.ay2(ay2_audio), .ay2(ay2_audio),
.audio(audio_out) .audio(audio_out)
); );
endmodule endmodule

2
cores/bitgen.bat Normal file
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@ -0,0 +1,2 @@
call mypath
%mypath%\bitgen.exe %*

2
cores/map.bat Normal file
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@ -0,0 +1,2 @@
call mypath
%mypath%\map.exe %*

2
cores/mypath.txt Normal file
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@ -0,0 +1,2 @@
rem put the correct path and rename this file to .bat
set mypath=C:\path_to\Xilinx\14.7\ISE_DS\ISE\bin\nt64

2
cores/ngdbuild.bat Normal file
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@ -0,0 +1,2 @@
call mypath
%mypath%\ngdbuild.exe %*

2
cores/par.bat Normal file
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@ -0,0 +1,2 @@
call mypath
%mypath%\par.exe %*

2
cores/trce.bat Normal file
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@ -0,0 +1,2 @@
call mypath
%mypath%\trce.exe %*

2
cores/xst.bat Normal file
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@ -0,0 +1,2 @@
call mypath
%mypath%\xst.exe %*

54
firmware/firmware.asm
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@ -51,7 +51,8 @@
; inputs lo: cursor position hi: max length ; inputs lo: cursor position hi: max length
; otro lo: pagina actual hi: mascara paginas ; otro lo: pagina actual hi: mascara paginas
define sdhc $8fd4 define sdhc $8fd4
define empstr $8fd5 define scnbak $8fd5
define empstr $8fd6
define config $9000 define config $9000
define indexe $a000 define indexe $a000
define active $a040 define active $a040
@ -214,8 +215,16 @@ keytab defb $00, $7a, $78, $63, $76 ; Caps z x c v
start ld bc, chrend-runbit start ld bc, chrend-runbit
ldir ldir
wreg scandbl_ctrl, $80
call loadch call loadch
ld a, scandbl_ctrl
ld bc, zxuno_port
out (c), a
inc b
ld a, (outvid)
scf
rra
ld (scnbak), a
out (c), a
im 1 im 1
ld de, fincad-1 ; descomprimo cadenas ld de, fincad-1 ; descomprimo cadenas
ld hl, finstr-1 ld hl, finstr-1
@ -262,7 +271,7 @@ start3 ld a, b
jr z, start3 jr z, start3
ld b, $13 ld b, $13
ldir ldir
ld bc, zxuno_port ; print ID ld bc, zxuno_port
out (c), a ; a = $ff = core_id out (c), a ; a = $ff = core_id
inc b inc b
ld hl, cad0+6 ; Load address of coreID string ld hl, cad0+6 ; Load address of coreID string
@ -1284,9 +1293,13 @@ upgra ld bc, (menuop)
ld d, 7 ld d, 7
upgra1 push af upgra1 push af
call help call help
ld de, $0200 | cad60>>8
ld hl, cmbpnt
pop af pop af
jr nz, upgra15
ld bc, $1806
ld ix, cad116
call prnmul
upgra15 ld de, $0200 | cad60>>8
ld hl, cmbpnt
jr nz, upgra2 jr nz, upgra2
ld (hl), cad60 & $ff ld (hl), cad60 & $ff
inc l inc l
@ -1311,7 +1324,7 @@ upgra3 ld a, ixl
inc l inc l
ld (hl), bnames>>8 ld (hl), bnames>>8
inc l inc l
ld (ix+23), b ld (ix+22), b
add ix, bc add ix, bc
ld a, (ix+31) ld a, (ix+31)
cp ' ' cp ' '
@ -3985,12 +3998,24 @@ l3ec3 ld a, ixl
in l, (c) in l, (c)
jp (hl) jp (hl)
block $3eff-$ ; 50 bytes block $3ee6-$ ; 25 bytes
lbytes ld a, (scnbak)
and %01111111
call setvid
call lbytes2
ld a, (scnbak)
setvid ld l, scandbl_ctrl
ld bc, zxuno_port
out (c), l
inc b
out (c), a
ret
l3eff in l,(c) l3eff in l,(c)
jp (hl) jp (hl)
lbytes di ; disable interrupts lbytes2 di ; disable interrupts
ld a, $0f ; make the border white and mic off. ld a, $0f ; make the border white and mic off.
out ($fe), a ; output to port. out ($fe), a ; output to port.
push ix push ix
@ -4158,7 +4183,7 @@ decbhl dec hl
block $7e00-$ block $7e00-$
cad0 defb 'Core: ',0 cad0 defb 'Core: ',0
cad1 defm 'http://zxuno.speccy.org', 0 cad1 defm 'http://zxuno.speccy.org', 0
defm 'ZX-Uno BIOS v0.328', 0 defm 'ZX-Uno BIOS v0.40', 0
defm 'Copyleft ', 127, ' 2016 ZX-Uno Team', 0 defm 'Copyleft ', 127, ' 2016 ZX-Uno Team', 0
defm 'Processor: Z80 3.5MHz', 0 defm 'Processor: Z80 3.5MHz', 0
defm 'Memory: 512K Ok', 0 defm 'Memory: 512K Ok', 0
@ -4193,7 +4218,7 @@ cad8 defm $10, ' ', $10, ' ', $10, 0
cad9 defb $14, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11 cad9 defb $14, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11
defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $18, $11 defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $18, $11
defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $15, 0 defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $15, 0
defb ' BIOS v0.328 ', $7f, '2016 ZX-Uno Team', 0 defb ' BIOS v0.40 ', $7f, '2016 ZX-Uno Team', 0
cad10 defb 'Hardware tests', 0 cad10 defb 'Hardware tests', 0
defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11 defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11
defb $11, $11, $11, $11, 0 defb $11, $11, $11, $11, 0
@ -4496,6 +4521,15 @@ cad114 defb 'Break to exit', 0
cad115 defb 'Slot occupied, select', 0 cad115 defb 'Slot occupied, select', 0
defb 'another or delete a', 0 defb 'another or delete a', 0
defb 'ROM to free it', 0 defb 'ROM to free it', 0
cad116 defb '2', 0
defb '3', 0
defb '4', 0
defb '5', 0
defb '6', 0
defb '7', 0
defb '8', 0
defb '9', 0, 0
;cad199 defb 'af0000 bc0000 de0000 hl0000 sp0000 ix0000 iy0000', 0 ;cad199 defb 'af0000 bc0000 de0000 hl0000 sp0000 ix0000 iy0000', 0
fincad fincad

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firmware/rom_taps/rooted.tap Normal file
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